Hynix Semiconductor Inc.

Other

Cha Deok Dong

Sang Wook Park

Seung Woo Shin

Il Keoun Han

Cheol Mo Jeong

Dong Jin Kim

Seung Cheol Lee

Jung Geun Kim

Whee Won Cho

Kwang Chul Joo

Suk Joong Kim

Ho Min Son

Ii Keoun Han

Jung Gu Lee

Sang Soo Lee

Noh Yeal Kwak

Hyun Soo Shon

Se Ho Park

Woo Ri Jeong

A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

Method of forming isolation layer in semiconductor device

An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved.

Method of forming isolation layer of flash memory device

A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Method of forming isolation layer of semiconductor device

The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.

Flash memory device and method of fabricating the same

A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting an etching process for trench. Thus, the present invention prevents the effect of thinning tunnel oxide film while reducing a critical dimension of an active region. And, it is possible to assure a normal cell operation by the Fowler-Nordheim (FN) tunneling effect owing to preventing the thinning tunnel oxide film.

Method for manufacturing flash memory device

A method of manufacturing a nonvolatile memory device is disclosed. The method includes the steps of forming a tunnel oxide layer, a first conductive layer for a floating gate, and a hard mask layer over a semiconductor substrate, etching a portion of the hard mask layer, the first conductive layer, the tunnel oxide layer and the semiconductor substrate, forming trenches, gap-filling the trenches with an insulating material to form isolation layers, removing the hard mask layer, forming second conductive layer for a floating gate on the entire surface, forming spacers on vertical faces of the second conductive layer, removing the second conductive layer on the isolation layers and between the spacers by means of an etch process using the spacers as etch masks, removing the spacers, and forming a dielectric layer and a third conductive layer on the entire surface including the second conductive layer. The method reduces the interference capacitance between neighboring word lines, minimizes the interference phenomenon, and minimizes the distributions of the program threshold voltage Vth between word lines.

Method of manufacturing nonvolatile memory device

A flash memory device and a method of manufacturing the same, the flash memory device includes isolation layers formed in an isolation region of a semiconductor substrate, an auxiliary oxide layer formed on edge portions of an active region of the semiconductor substrate and on protruded sidewalls of the isolation layers, a tunnel oxide layer formed on the auxiliary oxide layer of the edge portions of the active region and at a central portion of the active region, and a first polysilicon layer for a floating gate formed on the tunnel oxide layer.

Flash memory device and method of manufacturing the same

A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.

Semiconductor device and method of manufacturing the same

Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Accordingly, the interfacial properties of the polysilicon film can be improved. It is thus possible to improve an operating characteristic of a device by prohibiting concentration of an electric field at the portion.

Method of forming polysilicon layer in semiconductor device

A method for forming a gate electrode in the semiconductor device is disclosed. The disclosed methods for forming a gate electrode in a semiconductor includes forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the disclosed methods, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten suicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.

Method of forming gate electrode in semiconductor device

A method of fabricating a flash memory devices disclosed wherein, upon formation of sidewall oxide films, a regrown thickness of a screen oxide film is controlled. The width of an element isolation film is reduced by means of an etch process for removing the re-growth oxide film. This allows a floating gate space to be easily secured, and a thickness of the sidewall oxide films is reduced by means of a liner nitride film pre-treatment cleaning process. It is thus possible to secure the trench space, which facilitates gap-filling.

Method of fabricating flash memory device

The present invention relates to a method for forming an isolation film in a semiconductor device. After a trench for isolation is formed, a polymer film is stripped by a post cleaning process using BFN. A pre-treatment cleaning process using only SC-1 is performed and a sidewall oxidization process is then carried out. It is therefore possible to improve fail of the roughness of the trench sidewall and to easily strip polymer. Furthermore, since a conventional PET process is omitted, an isolation film manufacturing process is simplified. It is also possible to prohibit out-diffusion of dopants injected into a semiconductor substrate through a pre-treatment cleaning process using CLN N before the sidewall oxidization process. Incidentally, by forming a slope at the top corner of the trench, it is possible to prevent a gate oxide film thinning phenomenon that the gate oxide film thinner than a desired thickness is deposited at the trench corner. It is also possible to improve electrical properties of a device since an active region as much as a target critical dimension is secured.

Method of forming isolation film in semiconductor device

Disclosed is a method for manufacturing a capacitor of a semiconductor device. The method includes the steps of providing a substrate having a storage node plug, forming a PE-TEOS layer and a hard mask exposing a storage node contact area on the substrate, forming a storage node contact having a side profile of a positive and negative pattern through etching the PE-TEOS layer, removing the hard mask by etching-back the hard mask, performing an annealing process with respect to a resultant structure, forming a silicon layer on the silicon substrate, which passes through the annealing process, coating a photoresist film on an entire surface of the substrate, forming a storage node electrode by etching-back the photoresist film and the silicon layer, removing a remaining photoresist film, and forming a dielectric layer and a silicon layer on a storage node electrode structure.

Growing community of inventors

Ichon-shi, South Korea

Cha Deok Dong