Texas Instruments Corporation

Cetin Kaya

Michael Lueders

Johan Tjeerd Strydom

Howard L Tigelaar

Paul L Brohlin

Kemal Tamer San

Rabah Mezenner

Wayland B Holland

Yong Xie

Freidoon Mehrad

David K Liu

Nathan Richard Schemm

Maik Peter Kaufmann

James Teng

Wei William Lee

Sreenath Unnikrishnan

Claus Niels Neesgaard

Shifeng Zhao

Michael Lüeders

John Frederic Schreck

David J McElroy

Richard K Hester

Adam Lee Shook

Reima Tapani Laaksonen

Stephen Keith Heinrich-Barna

Ramesh Chandrasekaran

Stanton Petree Ashburn

Qiong M Li

Julian Zhiliang Chen

Klaus Krogsgaard

Serkan Dusmez

Men-Chee Chen

Karim Thomas Taghizadeh Kaschani

Sarma S Gunturi

Lieyi Fang

Daty Michael Rogers

Jeff Berwick

Kyle A Picone

Gill Manzur

Rana Lahiry

Mauzur Gill

Friedoon Mehrad

Michael Lüders

Michael Pate

A short circuit detection circuit includes a current terminal, a sense resistor, an amplifier, and a resistor-capacitor ladder. The sense resistor is coupled to the current terminal, and is configured to develop a sense voltage proportional to a current through the current terminal. The amplifier is coupled to the sense resistor, and is configured to generate a scaled current proportional to the sense voltage. The resistor-capacitor ladder is coupled to the amplifier, and is configured to generate a measurement voltage that represents a surface temperature rise due to the current through the current terminal.

Transistor short circuit protection

Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Synchronous bootstrap half bridge rectifier

An IC, comprising a first rail supply, a second rail supply, an external pad coupled to one of the first rail supply and the second rail supply, and an ESD protection circuit coupled to the external pad. The ESD protection circuit includes a slew rate detector coupled to the external pad, an amplifier coupled to an output of the slew rate detector, a one-shot coupled to an output of the amplifier, and a clamp circuit coupled an output of the one-shot.

Integrated circuit with electrostatic discharge protected power supply

A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.

Enhancement mode startup circuit with JFET emulation

Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

Methods, apparatus, and systems to drive a transistor

Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

Gate drivers and auto-zero comparators

Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.

Apparatus and methods to parallelize transistors

Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

High low power converter switches, latch, diode isolated intermediate ground

In described examples, a first power switching circuit receives a power switching control signal and activates a first power switch in response to the power switching control signal. A second power switching circuit receives the power switching control, activates a second power switch in response to the power switching control signal, and determines a first power switching delay in response to temperature indications of the first and second power switches. The second power switching circuit activates the second power switch at a first delayed time after the activation of the first power switch, where the first delayed time follows the activation of the first power switch by the determined first power switching delay.

Parallelling multiple power switches

A current sensor includes a die and a shunt resistor having a first temperature coefficient and having a first node and a second node fabricated onto the die, wherein the shunt resistor is for passing the current that is to be sensed. A first compensation resistor is fabricated onto the die and is coupled to the first node of the shunt resistor, wherein the first compensation resistor is proximate the shunt resistor and has a temperature coefficient that is similar to the temperature coefficient of the shunt resistor. A second compensation resistor is fabricated onto the die and is coupled to the second node of the shunt resistor, wherein the second compensation resistor is proximate the shunt resistor and has a temperature coefficient that is the close to the temperature coefficient of the shunt resistor.

Current sensor

A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.

Methods, apparatus, systems and articles of manufacture are disclosed to control parallel transistors. An example system includes a first transistor coupled in parallel to a second transistor, a pulse width modulation generator coupled to the first transistor. The pulse width modulation generator is to generate a first signal. The example system further includes a first switch timing controller coupled to the pulse width modulation generator. The first switch timing controller is to compare a first peak current of the first transistor with a second peak current and generate a second signal based on the comparison of the first peak current and the second peak current. The example system further includes a gate driver coupled to the first switch timing controller and the gate driver is to control the first transistor in response to the second signal.

Delaying turn on time to transistor comparing global, peak current

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Plano, TX, United States of America

Cetin Kaya