Infineon Technologies Ag

Infineon Technologies Austria Ag

Capital One Services, LLC

Cesare Buffa

Andreas Wiesbauer

Luis Hernandez-Corporales

Constantin Crisu

Richard Gaggl

Alessandro Caspani

Andres Quintero Alonso

Fernando Cardes Garcia

Bernhard Winkler

Dan-Ioan-Dumitru Stoica

Carlos Andres Perez Cruz

Enrique Prefasi

Andrea Baschirotto

Franz Michael Darrer

Elmar Bach

Victor Popescu-Stroe

Constantin Stroi

Mihai-Liviu Tudose

Vlad Buiculescu

Fulvio Ciciotti

Francisco Javier Perez Sanjurjo

Bernhard Kuttin

Andrés Quintero Alonso

Dan Ioan Dumitru Stoica

Matthias Böhm

A capacitive sensor includes a first conductive structure and a second conductive structure that form a first capacitor having a first capacitance that changes in response to an external force acting thereon and includes a MEMS output configured to output a first sense signal representative of the first capacitance; a second capacitor coupled to the MEMS output and configured to output a second sense signal based on the first sense signal; an amplifier comprising an amplifier input and configured to output an amplified signal based on the second sense signal; and a diagnostic circuit configured to receive two measurement signals, generate an offset measurement based on the two measurement signals, and detect a fault on a condition that the offset measurement is outside of a threshold range.

Diagnosis of electrical failures in capacitive sensors

A sensor circuit, having a startup phase and an operation phase, includes: a sensor configured to generate a sensor signal based on a measured property, wherein the sensor signal has a frequency spectrum defined by a first frequency and a second frequency that is greater than the first frequency; a signal processing circuit including an analog-to-digital converter (ADC) configured to convert the sensor signal into a digital sensor signal; and an offset diagnosis circuit. The offset diagnosis circuit includes: a low pass filter having a cutoff frequency less than the first frequency and configured to generate a filtered signal based on the digital sensor signal; an offset register configured to store a startup signal value of the filtered signal during the startup phase; and an offset comparator circuit configured to set a threshold range based on the startup signal value for use during the operation phase.

Gain and offset diagnosis of analog-to-digital converters in sensor signal path

A capacitive sensor includes a first conductive structure; a second conductive structure that is counter to the first conductive structure, wherein the second conductive structure is movable relative to the first conductive structure in response to an external force acting thereon, wherein the second conductive structure is capacitively coupled to the first conductive structure to form a first capacitor having a first capacitance that changes with a change in a distance between the first conductive structure and second conductive structure; a signal generator configured to apply a first electrical signal step at an input or at an output of the first capacitor to induce a first voltage transient response at the output of first capacitor; and a diagnostic circuit configured to detect a fault in the capacitive sensor by measuring a first time constant of the first voltage transient response and detecting the fault based on the first time constant.

Detecting capacitive faults and sensitivity faults in capacitive sensors

A capacitive sensor includes a first electrode structure; a second electrode structure that is counter to the first electrode structure, wherein the second electrode structure is movable relative to the first electrode structure and is capacitively coupled to the first electrode structure to form a capacitor having a capacitance that changes with a change in a distance between the first electrode structure and second electrode structure; a signal generator configured to apply an electrical signal at an input or at an output of the capacitor to induce a voltage transient response at the output of capacitor; and a diagnostic circuit configured to detect a fault in the capacitive sensor by measuring a time constant of the first voltage transient response and detecting the fault based on the time constant and based on whether the first electrical signal is the pull-in signal or the non-pull-in signal.

Detecting sensitivity faults in capacitive sensors by using pull-in functionality

A readout circuit for resistive and capacitive sensors includes a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; and an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation.

Readout circuit for resistive and capacitive sensors

An analog-to-digital converter includes a ring oscillator having an input for receiving an analog signal, a coarse counter including a maximum length sequence generator having an input coupled to the output of the ring oscillator, a fine counter including a Johnson counter having an input coupled to the output of the ring oscillator, and a difference generator having a first input coupled to the output of the coarse counter, a second input coupled to the output of the fine counter, and an output for providing a digital signal corresponding to the analog signal.

Voltage controlled oscillator based analog-to-digital converter including a maximum length sequence generator

A high-ohmic circuit includes a plurality of high-ohmic branches coupled in parallel between a first node and a second node. Each of the plurality of high-ohmic branches includes a first plurality of series connected resistive elements forming a first series path from the first node to the second node, each of the first plurality of series connected resistive elements comprising a first diode-connected transistor. Each of the plurality of high-ohmic branches further includes a second plurality of series connected resistive elements forming a second series path from the first node to the second node, each of the second plurality of series connected resistive elements comprising a second diode-connected transistor. The high-ohmic circuit further includes a plurality of switches, each of the switches being coupled between a corresponding one of the plurality of high-ohmic branches and the second node.

System and method for high-ohmic circuit

In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

System and method for an oversampled data converter

According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

Capacitance determination circuit and method for determining a capacitance

An analog-to-digital converter includes a ring oscillator having an input for receiving an analog signal, a coarse Gray code counter having a first input coupled to a first output of the ring oscillator and a second input for receiving a clock signal, a fine counter having first inputs coupled to secondary outputs of the ring oscillator and a second input for receiving the clock signal, a first difference generator having an input coupled to the output of the coarse counter, a second difference generator having an input coupled to the output of the fine counter, and an adder having a first input coupled to the output of the first difference generator, a second input coupled to the output of the second difference generator, and an output for providing a digital signal corresponding to the analog signal.

Coarse-fine quantization architecture for multiphase VCO-based ADCs

Sensor devices and methods are provided where a test signal is applied to a capacitive sensor. Furthermore, a bias voltage is applied to the capacitive sensor via a high impedance component. A path for applying the test signal excludes the high impedance component. Using this testing signal, in some implementations a capacity imbalance of the capacitive sensor may be detected.

Capacitive sensor testing

In various embodiments, a circuit is provided. The circuit includes: a voltage biasing circuit coupled to a microelectro-mechanical system (MEMS) microphone sensor, the MEMS microphone sensor coupled to a driver circuit, and the driver circuit coupled to an oscillator-based ADC circuit. The oscillator-based ADC circuit may include an Nth order sigma-delta modulator, where N is an integer equal to or greater than 1.

Sigma delta modulator for sensors

The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.

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Villach, Austria

Cesare Buffa