Freescale Semiconductor,inc.

Motorola Corporation

North Star Innovations Inc.

Cesar M Garza

Wei E Wu

William James Taylor, Jr

William J Dauksher

Stanley Michael Filipiak

Kevin D Lucas

Bernard J Roman

James Edward Vasek

Kevin J Nordquist

William Louis Wilkinson

Pawitter J S Mangat

William D Darlington

Sungseo Cho

A method for patterning a substrate is provided, which comprises (a) providing a substrate; (b) applying a first layer comprising a first photo resist to the substrate; (c) applying a second layer comprising a second photo resist over the first layer; (d) patterning the second layer; and (e) inspecting the patterned second layer with an inspection tool; wherein at least one of the first and second layers comprises a contrasting agent which increases the contrast between the first and second layers to the inspection tool.

Metrology of bilayer photoresist processes

A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Method of making a semiconductor device using treated photoresist

A semiconductor process and structure () uses a disposable sidewall spacer () associated with lightly doped drain (LDD) transistors. The disposable sidewall spacers are efficiently removed by a gaseous fluorine ambient. Either molecular or atomic fluorine gas is used to remove a silicon germanium sidewall spacer with high selectivity to exposed insulating layers. This etch process is also isotropic. An additional benefit of using a gaseous fluorine ambient is incorporation of fluorine in isolation regions () surrounding the transistors, thereby reducing the dielectric constant. Improved insulating properties of the isolations regions can allow increased integration.

Semiconductor process for disposable sidewall spacers

A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.

Method of forming a rim phase shifting mask and using the rim phase shifting mask to form a semiconductor device

A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer

Growing community of inventors

Round Rock, TX, United States of America

Cesar M Garza