Intel Corporation

Cesar Galindo

Kerry Dean Tedrow

Jahanshir J Javanifard

Mase J Taub

Robert E Larsen

Chaitanya S Rajguru

Jahanshir J Jayanifard

An integrated circuit arrangement for providing operating voltages for a flash EEPROM memory array, which integrated circuit arrangement utilizes a plurality of charge pumps in a staggered output arrangement to generate a high voltage output while generating lower amounts of current from each individual charge pump so that the provision of the necessary current is integrated over the entire period of the voltage output. Unique circuitry is provided for regulating the value of the output voltage produced by the arrangement in response to variations in the output voltage produced.

Method and apparatus for controlling the output voltage provided by a

An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

System having multiple phase boosted charge pump with a plurality of

Method and apparatus for a two phase bootstrap charge pump

Apparatus for a two phase bootstrap charge pump

An integrated circuit arrangement for providing erase voltages to a flash EEPROM memory array including one charge pump for generating a first high voltage with substantial current which may be used for application to the source terminals of flash EEPROM memory cells during erase and to the gate terminals of flash EEPROM memory cells during programming, and another charge pump for generating a second lower voltage which may be used for application to the drain terminals of flash EEPROM memory cells during programming.

Method and apparatus for programming and erasing flash EEPROM memory

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Stockton, CA, United States of America

Cesar Galindo