Bell Communications Research, Inc.

Cesar A Johnston

Hung-Hsiang J Chao

David John Smith

Kenneth C Young, Jr

A method and system are provided for managing memory to reassemble data packets received from different virtual channels in an ATM network. The method and system recognizes that both reliable and best effort traffic must be supported by a network interface. The system makes use of a virtual First-In-First-Out (FIFO) concept that partitions RAM memory space into multiple FIFO queues. The virtual FIFOs can have different sizes, and can be allocated to connections depending on quality of service requirements. A dedicated embedded controller 721 to provide flexibility is used in the system, as well as Content Addressable Memory (CAM) devices 723,724, and external logic. The method and system can also be applied at ATM transmitters in the implementation of congestion control algorithms.

Method for partitioning memory in a high speed network based on the type

Method and system are provided for processing B-ISDN transfer protocols in a telecommunication system utilizing a generic ATM/AAL interface having a programmable electronic circuit. At the ATM Adaptation Layer (AAL), segmentation and reassembly, and convergence sublayer protocols have been developed to support the different service types to be handled. The interface facilitates a cost effective yet relatively simple broadband ATM/AAL terminal adapter that performs ATM and ATM Adaptation Layer processing in a very flexible manner. The terminal adapter handles several different transfer protocols (AAL types 1, 3, 4 and 5) using a single architecture on a per protocol data unit (PDU) basis and may be implemented using field programmable gate arrays and off-the-shelf components. The method and system is flexible enough to support changes in existing, new and future AAL/ATM standards.

Broadband ISDN processing method and system

To recover the service clock of a variable bit rate source (170) which generates data at a rate which is not proportional to a service clock (76), timing cells are generated. The timing cells are generated at a rate which is proportional to the service clock (76). The timing cells and data are transmitted via a network (100). At the receive-end, the data is stored in a buffer (82). A phase locked loop (90') generates a local clock signal in the form of a read signal which controls the rate at which the received data is read out of the buffer (82). The read signal produced by the phase locked loop (90') is proportional to the average rate at which timing cells are received at the receive-end. In this manner the signal which reads the data out of the buffer (82) at the receive-end approaches the service clock (76) at the source end.

Service clock recovery for variable bit rate services

A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.

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Chatham, NJ, United States of America

Cesar A Johnston