Seagate Technology Incorporated

Cenk Argon

Kinhing Paul Tsang

Thomas V Souvignier

Richard Martin Born

Gregory Lee Silvus

Peter Igorevich Vasiliev

Erozan Mehmet Kurtas

Ivana Djurdjevic

Alexander Kuznetsov

A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.

System for providing running digital sum control in a precoded bit stream

A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

System for precoding parity bits to meet predetermined modulation constraints

A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Communication channel with Reed-Solomon encoding and single parity check

An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Interleaver with linear feedback shift register

A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit ('RLL') constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Providing running digital sum control in a precoded bit stream using precoder aware encoding

A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.

Data communication system with multi-dimensional error-correction product codes

Low complexity pseudo-random interleaver

A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Growing community of inventors

Madison, WI, United States of America

Cenk Argon