Other

Cem I Duru&ouml;z

Yoshinori Shimizu

Taner E Ozcelik

Takayuki Ishida

Pattabiraman Subramanian

A digital video presentation system is provided with a decoder to decode full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, particularly buffer memory size and display type (NTSC or PAL), to host trick play command signals, and to information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Field display logic is informed of the to memory address of the next field to be displayed along with the attributes needed for affecting proper field display sequence, and flagging whether the memory is to be freed for use by the decoder as the field is being displayed and whether the decoder is to decode the next picture as the field is being displayed. Where memory is small, opposite field data can be output. Field sequence order is provided for output buffers in the range of from 0.53 to 0.67 frames in size, or a full frame in size. Buffer memory is optimized by maintaining tables of offset variables and accessing a fixed table of memory pointers as fields of data are being displayed. The offset data tables are identified to the display logic, which uses the data in the specified offset table to address rows of memory in which the consecutive rows of particular field to be displayed are stored. The decoder loads offset values into the offset tables as pictures are being decoded and rows of blocks of the picture are stored as memory becomes free.

Digital video decoding, buffering and frame-rate converting method and apparatus

A single-chip application specific integrated circuit provides autonomous management of playback of digital video and audio. The chip includes a digital video decoder and output system, and a central processing unit controlling said digital video decoder and output system. The central processing unit receives commands to establish a current playback state for management of playback of digital video and audio by said digital video decoder and output system, and responds to a video field synchronization signal and a current playback state, without external instruction, to determine whether to display digital video, whether to decode digital video for display, whether to repeat display of previously decoded digital video, and whether to skip over digital video prior to decoding digital video for output. By delivering commands to the central processing unit, the application specific integrated circuit can be caused to transition between playback states to provide desired playback of said digital video and audio.

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San Francisco, CA, United States of America

Cem I Duruöz

Growing community of inventors

San Francisco, CA, United States of America

Cem I Duru&ouml;z

Cem I Duruöz