International Business Machines Corporation

Globalfoundries Inc.

Cedric Lichtenau

Silvia Melitta Mueller

Mary Prilotski Kusko

Thomas Pflueger

Petra Leber

Stefan Payer

Michael Klein

Razvan Peter Figuli

Jonathan D Bradbury

Kerstin Claudia Schelm

Peter Altevogt

Satya R S Bhamidipati

Klaus Michael Kroener

Andreas Koenig

Reid T Copeland

Jens Kuenzer

Laith M AlBarakat

Timothy John Slegel

Eric M Schwarz

Steven R Carlough

Michael F Fee

Tilman Gloekler

Gero Dittmann

Andreea Anghel

Xin Guo

Raghu Gaurav GopalaKrishnaSetty

Martin Padeffke

Ronald J Frishmuth

Satya Rama S Bhamidipati

Martin Recktenwald

Norman Jay Rohrer

Preetham M Lobo

Andreas Wagner

Simon Weishaupt

Nicol Hofmann

Rolf Bernhard Hilgendorf

Srinivas V N Polisetty

Tina Babinsky

Anthony Saporito

Vijayalakshmi Srinivasan

Steven Michael Douskey

Kailash Gopalakrishnan

Peter Anthony Sandon

Jens Peter Seifert

Michael Fan Wang

Swagath Venkataramani

Bishop Chapman Brock

Sunil K Shukla

Timothy J Koprowski

Joachim Von Buttlar

Rolf B Hilgendorf

Santosh Balasubramanian

Hagen Schmidt

Holger Horbach

Jörg-Stephan Vogt

Pradeep N Chatnahalli

Puja Sethia

Alberto Garcia Ortiz

Andreas Schmid

Markus Lachenmayr

L'Emir Salim Chehab

Pavankrishna Ellore Ramesh

Sourabh Chougule

Gregory J Cook

Alper Buyuktosunoglu

Bulent Abali

Jakob Christopher Lang

Gregory William Alexander

William Eric Hall

Mack Wayne Riley

Gregory Scott Still

Wei Wang

Jonathan James DeMent

Elaine Rivette Palmer

Yulong Li

Christian Borntraeger

Juergen Haess

Jochen Preiss

Tobias Gemmeke

Rolf Fritz

Thomas Gentner

Thuyen Le

Jay Gerald Heaslip

Friedrich Schroeder

Ingemar Holm

Antje Mueller

Ralf Richter

Ralph C Koester

Erwin B Cohen

Osher Yifrach

Christoph Jaeschke

Markus Cebulla

Eberhard Pasch

Mathew I Ringler

Miles G Canada

Stefan Bonsels

Martin A Lutz

Alberto Garcia-Ortiz

Eric Mark Schwarz

Processing input data for transmittal to a data consumer such as an artificial intelligence engine is performed by arranging the input data into a uniform structure made up of sticks of data combined to form pages of sticks. A stick is any well-sized set of input data elements whereby the size of the stick is fixed. A masking pattern is established for sticks of data having certain ranges of invalid data for consumption of partial sticks while maintaining validity of the input data being transferred. The mask pattern is derived based on set-active-mask-and-value (SAMV) instructions. The derived mask pattern is carried forward for subsequent load instructions to the data consumer.

Padding input data for artificial intelligence accelerators

A computer-implemented method, computer system and a computer program product schedule a secure code segment on a processor core of a processing unit between threads, wherein the processing unit is executing a program code of operating instructions of a thread on the at least one processor core. The method comprises a first thread requesting exclusive secure execution of a secure code segment of the program code on the at least one processor core. The method also comprises checking the request based on a secure-operation parameter that controls a request for exclusive secure execution of a secure code segment. The method further comprises, if the secure-operation parameter is below a predefined threshold value, setting the at least one processor core to exclusive secure execution for the secure code segment and periodically resetting the secure-operation parameter. If the secure-operation parameter is not below the threshold, then the method switches to another thread.

Scheduling a secure code segment on a processor core of a processing unit

A combined function specified by an instruction is performed. The combined function includes a plurality of operations performed as part of one invocation of the combined function. The performing the combined function includes performing a matrix multiplication of a first tensor and a second tensor to obtain one or more intermediate results. The second tensor includes an adjusted weight tensor created using a multiplier. Values of a bias tensor are added to the one or more intermediate results to obtain one or more results for the combined function. The one or more results are at least a part of an output tensor.

Single function to perform combined matrix multiplication and bias add operations

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

Rounding hexadecimal floating point numbers using binary incrementors

Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

Accelerator trustworthiness

Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

Verifying the correctness of a leading zero counter

An indication of a function to be executed is obtained, in which the function is one function of an instruction and configured to perform multiple operations. A determination is made of an operation of the multiple operations to be performed, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships. The set of values and corresponding set of relationships are based on the operation to be performed. One set of values and corresponding set of relationships are to be used for the operation to be performed, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations.

Single function to perform multiple operations with distinct operation parameter validation

A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

Variable replacement by an artificial intelligence accelerator

An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

Exception summary for invalid values detected during instruction execution

A computer system configured to perform operations for validating memory access patterns of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on memory access patterns and storing memory accesses in a first table, and executing the static variant of the program instruction stream on the accelerator processing unit. During execution, the virtual addresses may be discarded and replaced by the addresses provided in the address translation list. The operations may include recording and storing every memory access of executing the static variant of the program instruction stream in a second table and comparing the memory access patterns stored in the second table to memory accesses patterns stored in the first table. Memory access patterns may be validated or discarded.

Validating memory access patterns of static program code

An instruction is executed to perform a query function. The executing includes obtaining information relating to a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

Instruction to query for model-dependent information

A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

Neural network processing assist instruction

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Vector convert hexadecimal floating point to scaled decimal instruction

An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

Vector string search instruction

Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

Instruction interrupt suppression of overflow exception

Growing community of inventors

Stuttgart, Germany

Cedric Lichtenau