Imec Vzw

Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Imec USA Nanoelectronics Design Center

King Abdulaziz City for Science and Technology

Katholieke Universiteit Leuven

Katholieke Universitiet

Katholieke Universiteit Leuven, K.u. Leuven Research & Development

Cedric Huyghebaert

Eric Beyne

Emily Gallagher

Ivan Pollentier

Marina Yurievna Timmermans

Philippe Vereecken

Anne S Verhulst

Geoffrey Pourtois

Hanns Christoph Adelmann

Stefan De Gendt

Steven Brems

Jae Uk Lee

Wilfried B Vandervorst

Marc Marcel Heyns

Rita Rooyackers

Wim Dehaene

Philippe M Vereecken

Thomas Hantschel

Christoph Adelmann

Rik Jonckheere

Amirhasan Nourbakhsh

Mark Heyns

Xubin Chen

Thomas Nuytten

Marina Mariano Juste

Stefan DeGendt

Daniele Leonelli

Jan Van Olmen

Alessandra Leonhardt

Cesar Javier Lockhart De La Rosa

Anh Khoa Lu

Alaa Abd-Elnaiem

Mirco Cantoro

Ken Verguts

Jan Vaes

Elie Schapmans

A spot on a layer of a 2D semiconductor material deposited on a substrate is irradiated so as to generate excitons, so that photons are emitted from the layer. The photoluminescence spectrum is recorded for different values of the charge carrier concentration in the layer. The modulation of the charge carrier concentration may be realized by modulating the output power of the light source used to irradiate the sample. The relation is recorded between the ratio of the photoluminescence intensity of a first peak in the spectrum related to radiative recombination from indirect bandgaps to the intensity of a second peak in the spectrum related to radiative recombination from direct bandgaps, and the carrier concentration. This relation is fitted to a model of the ratio that takes into account multiple recombination mechanisms, radiative and non-radiative. From this process, the trap density within the bandgap is derived.

Method for measuring the trap density in a 2-dimensional semiconductor material

According to an aspect of the present disclosure there is provided a method for forming an EUVL pellicle, the method comprising: coating a carbon nanotube, CNT, membrane, and mounting the CNT membrane to a pellicle frame, wherein coating the CNT membrane comprises: pre-coating CNTs of the membrane with a seed material, and forming an outer coating on the pre-coated CNTs, the outer coating covering the pre-coated CNTs, the forming of the outer coating comprising depositing a coating material on the pre-coated CNTs by atomic layer deposition.

Method for forming an extreme ultraviolet lithography pellicle

A method for protecting a photomask comprises: (i) providing the photomask, (ii) providing a border, (iii) depositing at least two electrical contacts on the border, (iv) mounting a film comprising carbon nanotubes on the border such that the film comprises a free-standing part, wherein after the mounting and depositing steps, the electrical contacts are in contact with the film, (v) inducing a current through the free-standing part of the film by biasing at least one pair of the electrical contacts, and (vi) mounting the border on at least one side of the photomask with the free-standing part of the film above the photomask.

Induced stress for EUV pellicle tensioning

The present disclosure relates to a method for forming a pellicle for extreme ultraviolet lithography, the method comprising: forming a coating of a first material on a peripheral region of a main surface of a carbon nanotube pellicle membrane, the membrane including a carbon nanotube film, arranging the carbon nanotube pellicle membrane on a pellicle frame with the peripheral region facing a support surface of the pellicle frame, wherein the support surface of the pellicle frame is formed by a second material, and bonding together the coating of the carbon nanotube pellicle membrane and the pellicle support surface by pressing the carbon nanotube pellicle membrane and the pellicle support surface against each other. The present disclosure relates also relates to a method for forming a reticle system for extreme ultraviolet lithography.

Method for forming a pellicle

The present disclosure relates to a method for forming a carbon nanotube pellicle membrane for an extreme ultraviolet lithography reticle, the method comprising: bonding together overlapping carbon nanotubes of at least one carbon nanotube film by pressing the at least one carbon nanotube film between a first pressing surface and a second pressing surface, thereby forming a free-standing carbon nanotube pellicle membrane. The present disclosure also relates to a method for forming a pellicle for extreme ultraviolet lithography and for forming a reticle system for extreme ultraviolet lithography respectively.

Method for forming a carbon nanotube pellicle membrane

The disclosed technology generally relates to preparing two-dimensional material layers, and more particularly to releasing a graphene layer from a template substrate. According to an aspect, a method of releasing a graphene layer includes providing a template substrate on which the graphene layer is provided, the method comprising: subjecting the graphene layer and the template substrate to a water treatment by soaking the graphene layer and the template substrate in water such that water is intercalated between the template substrate and the graphene layer; and subjecting the graphene layer and the template substrate to a delamination process, thereby releasing the graphene layer from the template substrate.

Method of releasing graphene from substrate

The present disclosure provides a lithographic reticle system comprising a reticle, a first pellicle membrane mounted in front of the reticle, and a second pellicle membrane mounted in front of the first pellicle membrane, wherein the first pellicle membrane is arranged between the reticle and the second pellicle membrane, and wherein the second pellicle membrane is releasably mounted in relation to the first pellicle membrane and the reticle.

Lithographic reticle system

A method for transferring a graphene layer from a metal substrate to a second substrate is provided comprising: providing a graphene layer on the metal substrate, adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer, treating the metal substrate having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate, transferring the graphene layer to the second substrate, and optionally reusing the metal substrate by repeating the aforementioned steps.

Method for transfering a graphene layer

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

Two-dimensional material semiconductor device

A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices having the cluster. The cluster and the template both have an interconnected region and an interconnection-free region.

Nanowire cluster and template and method for nanowire cluster formation

A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.

Graphene-based semiconductor device

A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel.

Tunnel field-effect transistor and methods for manufacturing thereof

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (), comprising active components on the surface of said substrate, depositing a top layer () of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening () at least through said top layer, filling said opening(s) at least with a first conductive material (), and performing a first CMP step, to form said first conductive structures (), etching at least one second opening () at least through said top layer, filling said opening(s) at least with a second conductive material (), and performing a second CMP step, to form said second conductive structures (), wherein the method comprises the step of depositing a common CMP stopping layer () on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The disclosure is equally related to devices obtainable by the method of the disclosure.

Method for producing interconnect structures for integrated circuits

Growing community of inventors

Heverlee, Belgium

Cedric Huyghebaert