Cadence Design Systems, Inc.

Cecile Nghiem

Thaddeus Clay McCracken

Ping-Chih Wu

Patrick John Eichenseer

Kit Lam Cheong

Jong-Chang Lee

Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Growing community of inventors

Union City, CA, United States of America

Cecile Nghiem