California Institute of Technology

Cecile D Jung-Kubiak

Goutam Chattopadhyay

Choonsup Lee

Imran Mehdi

Theodore J Reck

John J Gill

Robert H Lin

Ken B Cooper

Alejandro Peralta

Jose V Siles

Risaku Toda

Jose Vicente Siles Perez

Bertrand Thomas

Frank Greer

Daniel W Wilson

Karl Y Yee

Richard E Muller

Victor E White

Erich T Schlecht

Emmanuel Decrossas

James E Polk

Matthew R Dickie

Sofia Rahiminejad

Colleen M Marrese-Reading

John R Anderson

Nima Rouhi

David Gonzalez-Ovejero

Maria Alonso delPino

Maria A Del Pino

Nuria Llombart

A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.

Method for making antenna array

A phase shifter comprising an actuator coupled to a dielectric. When the dielectric is inserted into the waveguide in response to actuation by the actuator, the phase velocity of the incoming electromagnetic wave is decreased, resulting in a phase shift of the electromagnetic wave. A desired phase shift and a low insertion loss can be controlled by positioning of the dielectric and engineering the permittivity of the dielectric.

Low loss microelectromechanical system (MEMS) phase shifter

A modulated MTS antenna including a metasurface fabricated from metallized cylinders on a ground plane. The antenna structure can be designed to operate in the Gigahertz or Terahertz frequency band and to have a well defined directivity. The MTS antenna may be micromachined out of a silicon wafer using deep reactive ion etching (DRIE).

Low-profile and high-gain modulated metasurface antennas from gigahertz to terahertz range frequencies

Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/&#x2212;10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.

Micro-emitters for electrospray systems

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Wafer-to-wafer alignment method

A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

340 GHz multipixel transceiver

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Multi-step deep reactive ion etching fabrication process for silicon-based terahertz components

A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

On-chip power-combining for high-power schottky diode based frequency multipliers

Growing community of inventors

Pasadena, CA, United States of America

Cecile D Jung-Kubiak