Soitec

Cecile Aulnette

Nicolas Daval

Bich-Yen Nguyen

Rainer Klaus Krause

Konstantin Bourdelle

Frank Dimroth

Eric Guiot

Eric Mazaleyrat

Khalid Radouane

This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.

Multiple transfer assembly process

The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Method for forming a Ge on III/V-on-insulator structure

The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.

Manufacture of thin silicon-on-insulator (SOI) structures

The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal. The invention also relates to a laminated wafer fabricating method using the recycled substrate and to a recycled substrate in which the surface of a first region lies lower than the surface of the second region.

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Guilderland, NY, United States of America

Cecile Aulnette