American Telephone and Telegraph, Co.

At&t Information Systems Inc.

Lucent Technologies Inc.

Bell Telephone Laboratories

At&t Bell Laboratories

Agere Systems Inc.

Agere Systems Guardian Corp.

At+t Corp.

At&t Information Systems Inc. Bell Telephone Laboratories, Inc.

Cecil William Farrow

Robert Louis Cupo

Hong Jiang

Charles Albert Webb, Iii

Ahmad Khalid Aman

Agesino Primatic, Jr

Daniel J Udovic

Mohammad Shafiul Mobin

Yhean-Sen Lai

Kannan Rajamani

Kalavai Janardhan Raghunath

David G Shaw

Daniel Amrany

Jack Salz

William E Keasler, Jr

Vahid Marandi

Joseph Maruscsak

Kaylan Mondal

Kai-Chuen Wong

The convergence time of a blind, adaptive equalizer is shortened by using a tracking generator. The tracking generator comprises a smoothing filter which receives and smoothes a tap coefficient error estimate derived from an output data stream. Thereafter, a fraction of the smoothed estimate is generated. It is the use of this function of the smoothes estimate which allows the convergence time to be shortened.

Methods and devices for shortening the convergence time of blind, adaptive equalizers

A method of converting between a sampling rate associated with a first audio format and a second audio format includes up-sampling an input signal sampled at the sample rate associated with the first audio format. Then, the up-sampled signal is filtered as a function of a fractional delay to generate an output signal sampled at the sample rate associated with the second audio format. The fractional delay is computed from the sample rates associated with the first and second audio formats. In one embodiment, the sample rates that are converted between are associated with a compact disc format having a sample rate of about 44.1 kHz and a digital audio tape format having a sample rate of about 48 kHz. In such case, the input samples are preferably up-sampled by a factor of two and the samples are then preferably filtered in accordance with a third order six taps coefficient finite impulse response filtering technique. The methodology of the present invention permits sample rate conversion from the CD format to the DAT format and from the DAT format to the CD format without changing filter coefficients.

Methods and apparatus for providing sample rate conversion between CD and DAT

A method and apparatus are disclosed for numerically controlling a ring oscillator. The disclosed programmable period ring oscillator selectively switches pairs of inverters into or out of the ring oscillator to provide a desired frequency. In one implementation, a programmable period ring oscillator provides a range of five to nine inverters that may selectively be included in the ring oscillator in increments of two inverters. A frequency synthesizer is disclosed that aligns the phase of the programmable ring oscillator with a reference signal. The frequency synthesizer generates a phase difference signal that is that is representative of the phase difference between the reference signal and the ring oscillator output. The phase difference signal is utilized to correct the frequency of the ring oscillator, so that the mean phase of the ring oscillator corresponds to the mean phase of the reference signal. The state of all of the stages in the ring oscillator are sampled, to permit the phase of the ring oscillator to be measured to a fraction of one cycle.

Self-timed numerically controlled ring oscillator

A QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal. The continuously variable digital rate interpolators/decimators are configured at startup so as to produce output streams at the same programmed rational rate multiple of the nominal baud rate of the anticipated received data signal, assuming the fs sample timing offset adjustment stream provided by the timing recovery feedback element to be identically 0. The &ldquo;nominal&rdquo; fixed sampling rate fs of the received analog input signal need not be rationally related to the nominal baud rate of the anticipated received data signal.

Fixed clock based arbitrary symbol rate timing recovery loop

A method of efficiently demodulating and isolating a signal within a fixed possibly wider band spectral region, having any of a wide range of baud rates. The signal is sampled at a fixed, first frequency which remains fixed no matter what the baud rate. Thus, the sample rate does not necessarily correspond to the desired baud rate. The sampled signal is then demodulated and low pass filtered to create baseband samples at the first frequency, which are then subject to user-specified arbitrary rate change in a continuously variable interpolator/decimator (continuously variable digital delay (CVDD) device), and decimated by a programmable power of 2, to produce samples at a second frequency. The second frequency is preferably determined to be a whole number multiple of the desired baud rate, e.g., twice the desired baud rate. The samples are equalized to produce output symbols at the target baud rate. Based on this method, a demodulator can receive signals of varying bandwidth and baud rates at arbitrary spectral locations within a possibly wider bandwidth aggregate channel span, and can adapt its target baud rate for each signal to be the actual baud rate of the derived incoming data signal within the possibly wider bandwidth aggregate channel span.

Variable baud rate demodulator

A digital carrier recovery system includes at least two modes of operation, namely, an acquisition mode and a tracking mode. The bandwidth of the carrier recovery loop filter is different for the acquisition mode and the tracking mode. In the acquisition mode, the digital phase-locked loop seeks and locks to the long term frequency offset of the received carrier signal. In the tracking mode, the digital phase-locked loop tracks the instantaneous variations in the carrier phase. Switching between the acquisition mode and the tracking mode is realized digitally, and includes programmable hysteresis, resulting in optimal performance in the presence of signals having high levels of phase noise (jitter). More specifically, the carrier recovery loop filter &ldquo;locks&rdquo; to the pilot signal of an incoming signal, e.g., a vestigial side band (VSB) video signal, by employing a so-called digital vector tracking phase-locked loop that demodulates the VSB signal. The digital vector tracking phase-locked loop includes a complex filter, i.e., a so-called vector tracking filter, that very quickly locks to the pilot signal of the passband VSB signal and once locked to the pilot signal, switches to the tracking mode that provides significantly better tracking of phase noise. The demodulation is achieved by employing a complex multiplication of the incoming signal with a complex exponential sequence to obtain an in-phase (I-phase) component and a quadrature-phase (Q-phase) component. The complex exponential sequence is generated, in one embodiment, by employing a SIN/COS look up table that is driven by a phase difference signal generated by the digital vector tracking phase-locked loop. A residual direct current (dc) component in the I-phase component caused by the pilot signal is removed, resulting in a baseband I/Q signal. A technical advantage of this carrier recovery invention is that the bandwidth of the phase-locked loop filter can be different for the acquisition mode and the tracking mode. This allows for optimal performance in both the acquisition and tracking modes of operation.

Carrier recovery system

A digital timing recovery system advantageously employs both demodulated I-phase and Q-phase components to more accurately locate the synchronization signal of an incoming VSB signal. The Q-phase component is advantageously employed to detect the phase error. The use of the Q-phase component provides a more accurate measure of the phase error and results in a larger (wider) acquisition range for timing frequency offset. More specifically, the timing recovery system of this invention performs symbol clock recovery based on the VSB signal segment synchronization (sync) signal and generates a pulse density modulated (PDM) phase difference signal that controls a voltage controlled crystal oscillator (VCXO) in the phase-locked loop. This is realized, in one embodiment of the invention, by correlating received sync segment data with the known sync signal pattern and searching for 'peaks' in the correlation values that are periodic at the known sync segment data rate. Once the sync pattern is found, the correlation values for adjacent samples are advantageously employed to generate the necessary feedback control signal value for the VCXO. Technical advantages of applicants' unique invention are that the need for an analog synchronous detector is eliminated, a more accurate measure than that obtained by prior known systems is obtained and a wider acquisition range is obtained for timing frequency offset.

Timing recovery system

A new filter that may be employed in timing recovery circuits, and automatic gain control circuits, employs a so-called vector tracking filter (VTF). The VTF includes a complex filter with a time constant so long that it might be considered a leaky integrator. In operation, the VTF builds up an average vector (timing (gain) estimate vector) having a direction that is the average of the estimated timing (gain) error, which is stored in the VTF. When the VTF is employed in an automatic gain control arrangement, the vector becomes a scalor and only the amplitude is tracked. When an arbitrary timing (gain) correction is made, to the incoming signal, this causes a rotation of the timing (gain) estimate vector. In order to track this rotation, a comparable rotation is made to the stored timing (gain) estimate vector. This allows the stored timing (gain) estimate vector to build up, and at any time the stored timing (gain) estimate vector will be the same as if the current incoming phase had been constant for all previous time. Consequently, it is possible to use a very long time constant in the VTF for long-term steady timing (gain) and at the same time acquire timing (gain) fast. In one example, the length of the vector stored in the VTF is allowed to build up until it reaches the mean value of the incoming timing (gain) estimate.

Vector tracking filter

Timing recovery circuits, automatic gain control circuits and the like, employ a so-called vector tracking filter (VTF) in conjunction with other timing recovery techniques. The VTF includes a complex filter with a time constant so long that it might be considered a leaky integrator. In operation, the VTF builds up an average vector (timing (gain estimate vector) having a direction that is the average of the estimated timing (gain) error, which is stored in the VTF. When an arbitrary timing (gain) correction is made, to the incoming signal, this causes a rotation of the timing (gain) estimate vector. In order to track this rotation, a comparable rotation is made to the stored timing (gain) estimate vector. This allows the stored timing (gain) estimate vector to build up, and at any time the stored timing (gain) estimate vector will be the same as if the current incoming phase had been constant for all previous time. Consequently, it is possible to use a very long time constant in the VTF for long-term steady timing (gain) and at the same time acquire timing (gain) fast. In one example, the length of the vector stored in the VTF is allowed to build up until it reaches the mean value of the incoming timing (gain) estimate.

Timing recovery arrangement

An incremental phase shifter for digital signals adapted to combine weighted amount of two quadrature square waves so as to generate a wave having a phase intermediate the respective phases of the two quadrature square wave signals. The generated wave is then processed in a limiting and integrating circuit so as to produce a square wave which is linearly related to the assigned weighted amounts of the two quadrate square waves.

Digitally controlled high resolution hybrid phase synthesizer

Timing recovery circuitry for recovering digital data generates a timing signal which is a function of the delay provided by an equalizer to one or more predetermined frequency components of its input signal. Advantageously, this approach is applicable to systems which utilize one or more baseband or passband equalizers. The disclosed embodiments of the present invention pertain to a dual-duplex system. In such a system, the digital data to be transmitted is divided into two different digital signals and each signal is coupled through an associated transmission channel. At the receiver, the received version of each transmitted signal is processed by an associated equalizer and the outputs therefrom are combined to recover the digital data. In the disclosed embodiments of the present invention, the necessary timing signal for such recovery is a function of the delay introduced by each equalizer to at least one predetermined frequency component of that equalizer's input signal.

Equalizer-based timing recovery

In a dual-duplex system wherein the communications channels have associated propagation delays which are typically different from one another, equalizers are connected to operate upon the signal received from each channel. To synchronize the operation of these equalizers to each other, the coefficients of each equalizer are updated when the training sequence is received from at least one of the communications channels. The sequence of symbol values in the training sequence may either be known or unknown to the receiver prior to transmission. When this sequence is detected, the coefficient updating circuit for each equalizer operates in response to a common reference signal. This reference signal includes a plurality of symbols and the value of each symbol is supplied at the same time to each equalizer coefficient updating circuit. This technique generates coefficients which compensate for propagation delay differences between the communications channels and is applicable to communications systems wherein data is distributed and transmitted through a plurality of communications channels.

Synchronizing the operation of multiple equilizers in a digital

A rational rate generator circuit is disclosed where the output signal frequency, f.sub.o, is rationally related to the input signal frequency, f.sub.i, by: f.sub.o =f.sub.i (P/Q). This rational rate generator is capable of a high-resolution output, where the resolution is only limited by the value of the integers P and Q, with P&lt;Q.

Rational rate frequency generator

The process of interpolating between two different sampling rates at any point in a sampling interval is obtained using a transversal filter arranged as a continuously variable digital delay line in which the tap coefficients of the delay line are made to be a function of the coefficients of an nth degree polynomial and the delay between the two sampling rates.

Growing community of inventors

Highlands, NJ, United States of America

Cecil William Farrow