Nec Electronics Corporation

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Nec Corporation

Cecil W Conkle

Noriaki Takagi

Masahiko Shoji

Qazi A Mahmood

Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.

Phase-locked loop timing controller in an integrated circuit memory

The present invention incorporates a control mechanism in an input buffer for a gate array so that the input buffer may be directly enabled or disabled by a control signal. Hence, no power will be wasted by the unnecessary operation of gates internal to the input buffer or subsequent stages. The method of control is to couple a common control signal to one input port of each of a plurality of two-input AND gates and couple an incoming data signal to the other input port of each of the two-input AND gates. The AND gates function as input buffers and the outputs of the AND gates are applied to the subsequent stage (e.g., a gate array). Thus, a LOW control signal disables the AND gate input buffers and subsequent stages coupled to the outputs of the AND gates, regardless of whether the incoming data signals are of a HIGH or LOW state.

Power saving input buffer for use with a gate array

A read only memory (ROM) includes a series of bit lines biased by a reference voltage lead (102). The reference voltage lead (102) is connected to a first reference voltage generator (100) having an output impedance of 25 ohms and a second reference voltage generator (104) having an output impedance of 75,000 ohms. When the ROM is deselected, the first reference voltage generator (100) turns off and the bit lines are biased by the second reference voltage generator (100). However, when the ROM is selected, the first reference voltage generator (100) is turned on and biases the bit lines. In this way, a ROM is provided which can operate in a low power mode without decreasing the access time when the ROM goes from a deselected state into a selected state.

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Palo Alto, CA, United States of America

Cecil W Conkle