Other

Plus Logic, Inc.

Signetics

U.S. Philips Corporation

Cradle Technologies, Inc.

North American Philips Corp., Signetics Div.

Plug Logic, Inc.

Cecil H Kaplinsky

Craig A MacKenna

Martin Freeman

Jan-Kwei J Li

Dirk H Braune

Theodor Mulder

Gunther A Zimmer

A multiprocessor computer system in which each processor being used as a target device has a FIFO (first in first out) buffer for receiving and storing transfer commands from a split transactional global bus for later execution. The transfer commands are put in the FIFO of the target device in the order of their arrival and are taken out of the FIFO and executed by the target device in the same order. This eliminates the wasting of bus time that occurs when busy signals are sent from target devices to master devices and when transfer commands are resent from master devices to target devices. Therefore, the present invention eliminates the wasting of bus time related to transfer commands being rejected.

Multiprocessor computer systems with command FIFO buffer at each target device

Configurable I/O circuitry having a plurality of configurable input/output elements, each of which connects one of a plurality of bits of a data bus to a corresponding one of the input/output terminals. Multiple clock selects and programmable enable signals can be connected to different interface elements to control activation of the interface element to which it is connected. The activated interface elements make up a virtual port that can be of any arbitrary bit width that is less than or equal to the fixed width of a physical port. This allows virtual ports on the data bus to be constructed that are narrower than the physical ports so that narrower data can be utilized in the port without causing the potential use of any of the data pins to be lost.

Configurable I/O circuitry defining virtual ports

A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.

Low power, static content addressable memory

In a system of plural bus driver circuits connected to a shared bus line, each of the driver circuits has combinatorial logic responsive, driving a final clock cycle for an active driver, to the difference between the data input and output of a tri-state driver element so as to generate a control signal that maintains the driver element in a active state until the data input and output are identical and then providing early release of the driver element to an inactive state, so that the next driver circuit can be activated at the start of the next clock cycle without conflict.

Driver circuit providing early release and quick bus turn-around

A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

Inverter-controlled digital interface circuit with dual switching points

A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state. Since neither the latch or output enable control, nor the latch elements themselves, are signal delaying components in the main signal path from the buffer input to the buffer output, throughput speed is not adversely affected.

Tristate buffer circuit with transparent latching capability

A programmable logic device in accordance with the present invention includes a partially populated switch matrix for coupling a plurality of logic blocks. Having a partial switch matrix reduces the silicon area requirement of the device. In addition, the capacitive loading is reduced, which improves propagation speed and lowers the power requirement of the sense amps, since smaller sense amps can be used. Bypass means are provided to allow the propagation bit lines (i.e. carry and shift lines) to bypass one or more logic block. Each of the logic blocks includes a plurality of logic cells. Means are provided among the logic cells to provide bypass capability for the propagation lines among the logic cells. The logic cells feature means for reverse propagation of the carry and shift bits among the logic cells. The logic cells of the present invention also feature reverse propagation with bypass.

Programmable logic device with partial switch matrix and bypass mechanism

A dynamic termination circuit is disclosed that has a plurality of parallel termination elements that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dynamic resistive path between a voltage supply line and that termination element's output and a second dynamic resistive path between the termination element output and ground, both resistive paths including field-effect transistors whose control gates are responsive to a signal received from the transmission line via an input to the circuit. For successive response, a series of delay elements are provided between the circuit input and the respective termination circuit elements. For selective enablement, logic gates connected between the termination element inputs and the field-effect transistor control gates have enable inputs receiving user-programmable enable signals for the respective termination elements. In addition to the impedance provided by the main dynamic resistive paths to voltage supply and ground, at least one of the termination elements may have supplemental dynamic resistive paths in parallel with the main paths and responsive to a TRIM bit to allow adjustment of the actual impedance to manufacturing tolerances.

Programmable dynamic line-termination circuit

A buffer circuit includes a pair of pull-up output transistors and a pair of pull-down output transistors driving an output line. Each output transistor is driven by its own tristate input translator, all connected to an input terminal of the circuit. Two of the translators are tristated by control signals received as feedback from the output line to turn off one of the pull-up transistors when the output exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition. Because the output transistors are driven directly by the input translators, throughput speed is improved, while ramp rate of the translator outputs driving the output transistors can remain slow to reject input noise spikes and avoid generation of output noise.

Low noise tri-state output buffer

A buffer, driver, or level-shifting circuit having an input connected to signal inputs of a pair of comparators and an output connected between a pair of pull-up and pull-down transistors controlled by the comparators. A first reference voltage applied to the reference input of the comparator controlling the pull-up transistor is selected to be less than the nominal transition point of the circuit, while a second reference voltage applied to the reference input of the comparator controlling the pull-down transistor is selected to be greater than the nominal transition point of the circuit, thereby allowing the circuit to recognize the beginning of signal transitions on the its input sooner. The comparators are differential amplifiers which are enableable and disableable in response to a feedback signal from the circuit's output in order to reduce current consumption during transitions. When the output is high, the comparator controlling pull-down is enabled, while the comparator controlling pull-up is disabled. When the output is low, the comparator controlling pull-up is enabled, while the comparator controlling pull-down is disabled. Undershoot and overshoot control circuitry may be provided by replacing the single pull-up transistor, pull-down transistor, or both with pairs of parallel transistors whose combined conductance is comparable to that of the replaced transistor. One of the parallel transistors is turned off after the nominal transition point has been reached on the circuit's output, thus slowing pull-down or pull-up during the latter part of the transition when speed no longer matters.

Digital interface circuit with dual switching points for increased speed

A non-volatile memory connected to state logic is provided for autoloading peripheral target devices at power-on or system reset. The memory is preloaded with commands and data. At power-on or system reset the commands are executed in sequence, transferring data to selected target devices. Data is output in bit-serial fashion on a single line. Target devices are individually selected through use of separate clock lines. Clock signals on the clock lines can be internally generated using the state logic or a target-device-supplied clock can be received under program selection. The system reset signal is intercepted and retransmitted to control target device mode. System reset polarity, enable signal polarity, data block length, clock direction, internal clock frequency, and power-saving shutdown upon completion of all transfers are all programmably selectable features.

Memory system for loading peripherals on power up

A logic circuit having a programmable first logic circuit stage and a fixed or dedicated combinatorial second logic circuit stage, serving as a macrocell for the first logic circuit stage. At least one input to the logic circuit is connected directly to the second stage, bypassing the first stage. The first stage may be a programmable logic device with a programmable AND plane followed by an OR plane, and is functionally flexible. The second stage has at least two groups of CMOS logic gates arranged in sequence and connected in a fixed manner by hardwiring so as to implement a specified combinatorial logic function that is representable in sum-of-products form, and is fast compared to the first stage. The outputs from the first stage control logic operations of the second stage upon the directly connected input or inputs.

Fast CMOS logic with programmable logic control

A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output polarity. This programmable macrocell circuit has two master latch elements and one slave latch element. The master latch elements are respectively inverting and noninverting latches which are located on two parallel alternate paths. A set of pass transistors on the input end of the two paths causes an input signal to drive only a selected one of the two paths and its associated master latch element. A two-by-one multiplexer connects the output of the selected master latch element in one of the two signal paths to the input of the slave latch. The control signals for the set of pass transistors and the two-by-one multiplexer can be either clock signals or fixed logic level signals, the particular choice of signals determining whether the circuit operates as a flip-flop, latch, or transparent circuit, and the particular choice of signal paths determining the circuit's output polarity.

Programmable macrocell circuit

A clock distribution circuit with multiple clock drivers distributing a clock signal on multiple signal paths has active de-skewing logic circuitry for equalizing the total clock delay to the different clock recipient circuits in a system. The de-skewing logic uses a return path parallel to the outward signal path to sense the propagation delay and includes a phase comparator with inputs receiving the return signal and a reference signal for comparison of their phase. Voltage-controlled delay elements, responsive to a control voltage provided by a charge pump controlled by the phase comparator, adds or removes equal amounts of delay to the outward and return signal paths until the return signal phase matches that of the reference signal. Each clock driver may have its own de-skewing circuitry or may share a common reference signal. In one embodiment the de-skewing circuitry for each driver time-shares a common phase comparator and charge pump, using sample-and-hold circuits to store the control voltages obtained by the comparisons. Input receivers on the return paths may have selectable input buffers to take into account the different buffer delays of different logic family types of the clock recipients.

Clock distribution circuit with active de-skewing

A write assist circuit for CMOS inverter-type memory cells and latches having means for choking current flow from a voltage level source to power supply terminals of a group of such memory cells or latches during a data loading or write cycle. The write assist circuit has a pair of pass transistors that respectively connect to one or two voltage level sources. In one embodiment, both pass transistors connect in parallel to a single voltage level source, one transistor always active being of low conductance, the other transistor of normal conductance being turned off by a write enable signal. In another embodiment, both pass transistors are of normal conductance but are respectively enabled and disabled by a write enable signal and are connected to different voltage level sources so as to supply a lower power supply voltage to the CMOS inverter-type memory cells or latches during a write cycle.

Growing community of inventors

Palo Alto, CA, United States of America

Cecil H Kaplinsky