Texas Advanced Optoelectronic Solutions, Inc.

Ams Ag

Micro Linear Corporation

Semiconductor Components Industries, LLC

Level One Communications, Inc.

Cecil Aswell

Eugene G Dierschke

Gonggui Xu

Ken McBride

Lloyd Hasley

Stefan M Wurster

Lester L Hodson

John H Berlien, Jr

Haim Shafir

Mario Manninger

Daniel L Ray

David W Feldbaumer

Mark B Weaver

Joseph E Heideman

William W Wiles, Jr

Rimon Shookhtim

Cheng-chung Shih

A signal conditioning circuit for a light sensor, in particular for an ambient light sensor, comprises a first integration stage (INT) connected to a first sensor input (IN) to receive a first and second sensor signal and a second integration stage (INT) comprising a coupling input (IN) to receive from the first integration stage (INT) a first and second integrated sensor signal. A coupling stage (S, C) is connecting the first and second integration stages (INT, INT) and is designed to generate a difference signal from consecutively received integrated first and second integrated sensor signals. A sensor arrangement and a method for signal conditioning for a light sensor is also presented.

Signal conditioning circuit for a light sensor, a sensor arrangement and a method for signal conditioning for a light sensor

A light sensor arrangement according to the proposed principle comprises at least one first unshielded well (D) and at least one second shielded well (D) in a substrate (P). The at least one first unshielded well (D) is being exposed to incident light (&#x3bb;) and configured to generate a first sensor signal (Ch) as a function of the incident light (&#x3bb;). The at least one second shielded well (D) in the substrate (p) being shielded from the incident light (&#x3bb;) and configured to generate a second sensor signal (Ch) as a function of the incident light (&#x3bb;). The light sensor arrangement further comprises means for temperature compensation providing the first and second sensor signals (Ch, Ch) as temperature compensated sensor signals as a function of substrate temperature. Means to determine spectral content of the incident light (&#x3bb;) are provided to determine the spectral content as a function of the temperature compensated first and second sensor signals (Ch, Ch).

Light sensor arrangement and method for temperature compensation in a light sensor arrangement

Semiconductor structures for optoelectronic sensors with an infrared (IR) blocking filter and methods for using such sensors with post-detection compensation for IR content that passes through the IR blocking filter are provided herein.

Method and device for optoelectronic sensors with IR blocking filter

A circuit for calibrating optoelectronic devices automatically trims a light sensor based upon a known light condition.

Automatic calibration circuit for optoelectronic devices

A transimpedance amplifier includes a first amplifier, a first MOS resistor device and a first voltage divider circuit. The source terminal of the first MOS resistor device is coupled to the first amplifier inverting input. The voltage divider circuit is coupled between the first amplifier output and the non-inverting input. The output of the first voltage divider is coupled to the first MOS resistor drain terminal. A second amplifier, second MOS resistor device and a second voltage divider circuit is also provided. The output of the second amplifier is coupled to the gate terminal of the first MOS resistor device. The gate terminal of the second MOS resistor device is coupled to the second amplifier output. The drain terminal of the second MOS resistor device is coupled to the second amplifier non-inverting input. The second voltage divider circuit is coupled between the first amplifier output and the second MOS resistor device source terminal, and has an output coupled to the second amplifier inverting input.

Transimpedance amplifier

A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate near the rail of a circuit. Accordingly, a five terminal distributed MOS resistor device includes a drain terminal, a source terminal, and a channel region disposed between the drain terminal and the source terminal. A bulk terminal is adjacent the channel region. A first gate terminal is adjacent the source terminal and a second gate terminal is adjacent the drain terminal. Lastly, a gate region of resistive material is disposed between the first gate terminal and the second gate terminal, wherein upon application of a voltage to the first gate terminal and the second gate terminal, a voltage drop across the gate region is equally distributed along a length of an electrical channel in the channel region.

High sheet MOS resistor method and apparatus

A monolithic optical detector for determining spectral content of an incident light includes at least a first and second well in a substrate, the second well formed proximate the first well. The first well is configured to be exposed to incident light and for generating a first photocurrent as a function of the incident light. The second well is configured to be shielded from the incident light and for generating a second photocurrent as a function of the incident light. Lastly, a processing and control unit, responsive to the first and second photocurrents, determines an indication of spectral content of the incident light. A method and device parameter controller are also disclosed.

Method and apparatus for optical detector with special discrimination

A timing based adaptive equalization circuit ( ) dynamically monitors a signal received at an input terminal ( ) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit ( ) centers the transition of the equalized signal in a delay line circuit ( ). An analog delay locked loop circuit ( ) provides a fixed throughput time for matching delay elements of delay line circuits ( and ) in the adaptive equalization circuit ( ). Timing signals propagating in the delay line circuits ( and ) are stored in sampler circuits ( and ). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits ( and ).

Adaptive equalization circuit and method

A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.

Series terminated clock deskewing apparatus

A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances. A three input phase detector is coupled to a fixed delay line and to either the series terminated transmission line system or the Thevenin terminated transmission line system for eliminating phase shifts of the clock signals between the different loads.

Clock deskewing apparatus including three-input phase detector

A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.

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Orangevale, CA, United States of America

Cecil Aswell