Infineon Technologies Ag

Qimonda Ag

Altis Semiconductor, Snc

Adesto Technology Corporation

Cay-Uwe Pinnow

Klaus-Dieter Ufert

Thomas Happ

Ralf Symanczyk

Martin Gutsche

Michael Kund

Josef Willer

Wolfgang Raberg

Gerhard Mueller

Harald Seidl

Rainer Bruchhaus

Klaus Ufert

A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.

Method for producing memory having a solid electrolyte material region

An integrated semiconductor memory includes a storage medium () arranged between two electrodes (), which storage medium may be a phase change medium, for example. The storage medium () can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material () are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

Integrated circuit having a resistive memory

A solid electrolyte memory element comprising an inert cathode electrode, a reactive anode electrode and a solid electrolyte layer disposed between the inert cathode electrode and the reactive anode electrode, wherein the solid electrolyte layer comprises a solid electrolyte matrix having defect sites.

Solid electrolyte memory element and method for fabricating such a memory element

A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASeS. One component A of the chalcogenide compounds ASeScomprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Method for manufacturing an integrated circuit including an electrolyte material layer

According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.

Integrated circuit, method for manufacturing an integrated circuit, memory cell array, memory module, and device

Method for fabricating an integrated device, comprising the step of providing a substrate, which includes an electrode element, and a step of providing a solid electrolyte element coupled to the electrode element. The solid electrolyte element is provided in a crystalline state and in conjunction with electrode element such to form a programmable resistance element. The method furthermore comprises a heating process, after providing the solid electrolyte element.

Method for fabricating an integrated device comprising a structure with a solid electrolyte

A chalcogenide layer includes a composition of compounds having the formula MX, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers

A method for fabricating a solid electrolyte memory device comprises a plurality of solid electrolyte memory cells, the solid electrolyte memory cells sharing a common continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, the method comprising the process of introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

Method for fabricating a solid electrolyte memory device and solid electrolyte memory device

A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.

Solid electrolyte switching element

A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Integrated circuit including sub-lithographic structures

A non-volatile, resistively switching memory cell includes a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal which is distributed in the amorphous or partially amorphous, non-oxidic matrix and whose cations migrate to the cathode in the amorphous or partially amorphous, non-oxidic matrix under the influence of an electrical voltage, wherein the solid electrolyte contains one or more further metallic materials for stabilization of the amorphous state of the matrix.

Method for improving the thermal characteristics of semiconductor memory cells

The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.

Resistively switching memory

The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.

Memory device electrode with a surface structure

A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.

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Munich, Germany

Cay-Uwe Pinnow