Intel Corporation

Other

Cau L Nguyen

James P Kardach

Kameswaran Sivamani

Gregory Scott Mathews

Gurbir Singh

Xia Dai

Sung Soo Cho

Edwin J Pole, Ii

Edward S Zager

John T Orton

David S Vannier

Shing Wong

Nazar Syed Haider

Raviprakash Nagaraj

Ravi Nagaraj

Srinivasan Rajagopalan

Harini G Setlur

A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

Apparatus and method for changing processor clock ratio settings

An apparatus to identify a storage device of a processor within a digital system is described. The processor includes a first storage device designed to generate a first signal when the first storage device contains a copy of a requested entry in a main storage device. The first signal is in a first state when the copy is of a first type and is in a second state when the copy is of a second type. A second storage device is included that is designed to generate a second signal when the second storage device contains the copy of the requested entry in the main storage device. The second signal is in the first state when the copy is of the first type and is in the second state when the copy is of the second type. The processor also includes a first logic device that generates a first indicator signal in response to receiving the first signal, and is coupled to the first storage device. The indicator signals are representative of the storage device that contains. The processor is also designed such that the first indicator signal is applied to a first pin. A method for identifying a storage device in a processor includes generating a common signal on a bus in a digital system. A first indicator signal is generated in response to receiving a first signal from a first storage device. A second indicator signal is generated in response to receiving a second signal from a second storage device. The processor is identified as the originator of the common signal in response to analyzing the indicator signal and the common signal.

Method and apparatus to identify a storage device within a digital system

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Changing clock frequency

Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Slew rate control circuit

A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of interruption and a halt indicator indicating the CPU was interrupted from a halt state. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The halt state indicator is set by the added interrupt of the CPU is in a halt state at the time of interruption. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The Halt instruction is re-executed by the RESUME instruction if the halt state indicator remains set at the time of restoration. As a result, a system integrator or OEM may provide transparent system level interrupts with automated halt state restart that will operate reliably in any operating environment, and be relieved of the burden of managing halt state restart.

Transparent system interrupts with automated halt state restart

A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

Computer system with interrupts transparent to its operating system and

A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by the bus unit. A dedicated memory area is provided for storing a customizable system interrupt service routine, program state data at the time of interruption and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted and continued execution including automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.

Transparent system interrupts with automated input/output trap restart

A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, and processor state data at the time of interruption. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The extended memory addressing limits are overridden when the CPU is interrupted by this added interrupt. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The extended memory addressing limits are restored when the CPU is restored by the RESUME instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with integrated extended memory addressing that will operate reliably in any operating environment, and be able to address the entire physical address space and have access to all system resources in a stand alone manner during the interrupt.

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Fremont, CA, United States of America

Cau L Nguyen