Microsemi Semiconductor Ulc

Cathy Zhang

Krste Mitric

Qu Gary Jin

Tanmay Zargar

Paul H L M Schram

Wenbao Wang

David Colby

Gabriel Rusaneanu

Paul Schram

Robertus Van Der Valk

In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Hardware delay compensation in digital phase locked loop

A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.

Phase locked loop with simultaneous locking to low and high frequency clocks

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Ottawa, Canada

Cathy Zhang