Lsi Corporation

Lsi Logic Corporation

Cathy Ye Liu

Freeman Yingquan Zhong

Yikui (Jen) Dong

Amaresh Virupanagouda Malipatil

Lizhi Zhong

Mark J Marlett

Joseph Caroselli

Charles E MacDonald

Philip N Jenkins

Jeff Kueng

Shao Ming Hsu

A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.

Band-pass high-order analog filter backed hybrid receiver equalization

A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.

Adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE)

An apparatus comprises a summer suitable for subtracting a filtered feedback signal from an input; a symbol decision device suitable for receiving an output from the summer; a feedback filter suitable for filtering an output from the symbol decision device and for sending the filtered feedback signal to the summer, the feedback filter comprising an adjustable swing amplifier and an adjustable pole filter; and an adaptation algorithm suitable for simultaneously adapting both a pole setting and a swing setting based upon a least mean squared error criteria. The summer, the symbol decision device, and the feedback filter form a feedback circuit utilized to reconstruct an electrical signal distorted during transmission.

Continuous time&#x2014;decision feedback equalizer

In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline wander compensation

The present invention is directed to a detector for a high-density magnetic recording channel and other partial response channels. The present invention presents a method for decoding a high rate product code and a decoder which uses this method, comprising receiving a high rate product code; using a row detector to find a most likely codeword and a most likely error sequence for each row; and using a column processor to correct any remaining errors based on column parity bits and the most likely error sequence of each row. In a first aspect of the present invention, the row detector is implemented through a 2-VA detector. In a second aspect of the present invention, the row detector is implemented through a conventional VA detector and a hank of matched filters.

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San Jose, CA, United States of America

Cathy Ye Liu