Texas Instruments Corporation

Cathy A Chancellor

Anand T Krishnan

Srikanth Krishnan

Vijay Kumar Reddy

Rajesh B Khamankar

Husam N Alshareef

Malcolm John Bevan

Ajith Varghese

A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Thermal treatment of nitrided oxide to improve negative bias thermal instability

Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

System and method for accurate negative bias temperature instability characterization

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Cathy A Chancellor