Sgs-thomson Microelectronics Limited

Inmos Limited

Catherine Louise Barnaby

Glenn Ashley Farrall

Nathan Mackenzie Sidwell

Richard J Gammack

Anthony I Stansfield

Bruno Fel

Andrew Craig Sturges

David May

Roger M Shepherd

A computer system has a processor, a cache and a main memory. A cache coherency mechanism ensures that the contents of the cache are coherent with respect to main memory by the provision of cache coherency instructions which each specify: 1) an operation to be executed on the contents of a location in the cache; and 2) an address in main memory. The operation is executed for the contents of the location in the cache which could be filled by an access to that address in main memory if the executing process normally has access to that address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache. This provides an extra degree of freedom because it is not necessary for the cache coherency operation to be requested in respect of a particular address stored in the cache. The instruction can specify any address which would map onto that cache location.

Cache coherency mechanism using an operation to be executed on the contents of a location in a cache specifying an address in main memory

A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

Cache system

A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called 'packed instructions'. Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganized within a data string thereby minimizing loading and storing operations to memory.

Manipulation of data

A video signal memory holds blocks of data representing luminance and first and second chrominance signals, the first and second chrominance signals being held in interleaved rows within the blocks, data being transferred from said blocks to a temporary store for use by a processor in predicting picture frames from the stored data.

Method and apparatus for interleaving chrominance signals in a video

A method of effecting a matrix transpose operation in a computer is described. The method uses a computer instruction which restructures a data string by retaining first and last sub-strings of the data string in unchanged positions and interchanges the position of at least two intermediate sub-strings. The data string is formed from sub-strings each representing one or more data value in a matrix. The computer instruction can be effected in a single register store having a predetermined bit capacity addressable by a single address, or in a pair of such register stores. The data restructuring instructions include 'flip', 'zip' and 'unzip' instructions.

Method for transposing multi-bit matrix wherein first and last

A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).

Cache memory system including a RAM for storing data and CAM cell arrays

A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the input data word with the stored data word occurs causing at least two cells in that row to change a signal level on a match line for that row, said memory accessing system being arranged to operate with a time delay for each associate operation which is less than that required for a single cell mismatch. The invention also provides a content addressable memory.

Cam with additional row cells connected to match line

A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch. The invention also provides digital signal comparison circuitry.

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Bristol, United Kingdom

Catherine Louise Barnaby