Xilinx, Inc.

Other

Catherine Hearne

Ronan Sean Casey

Kevin Zheng

Parag Upadhyaya

Hongtao Zhang

Declan Carey

Jinyung Namkoong

Lokesh Rajendran

John Martin Horan

Mayank Raj

John Anthony Keane

Gerard David Guthrie

Kevin Geary

Marc Erett

Vamshi Manthena

Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Ultra-high-speed PAM-N CMOS inverter serial link

Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

Integrated circuit including a continuous time linear equalizer (CTLE) circuit and method of operation

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Method and apparatus for clock phase generation

The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.

Method of implementing a differential integrating phase interpolator

A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Phase interpolator and method of implementing a phase interpolator

A self calibrating cable, including a USB3 cable, with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel. Additional embodiments provide for a selected replica boost device and a distinct pattern generator device in the calibration fixture. A corresponding system and method for calibrating a cable are also provided.

Growing community of inventors

Fermoy, Ireland

Catherine Hearne