Stmicroelectronics S.r.l.

Consiglio Nazionale Delle Ricerche

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Stmicroelectronics International N.v.

Cateno Marco Camalleri

Ferruccio Frisina

Mario Giuseppe Saggio

Angelo Magri′

Giuseppe Ferla

Angelo Magri'

Dario Salinas

Luigi Mariucci

Alfio Guarnera

Angelo Magri

Alfio Russo

Edoardo Zanetti

Simona Lorenti

Guglielmo Fortunato

Giuseppe Arena

Gabriele Bellocchi

Massimo Cuscuna

Massimo Cuscuna′

Caterina Donato

Denise Cali&prime;

Patrizia Vasquez

Giovanni Franco

Laura Letizia Scalia

A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof

Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device

A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.

Process for manufacturing a large-scale integration MOS device and corresponding MOS device

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

Method of manufacturing a semiconductor power device

A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200&deg; C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000&deg; C. with nitrogen protoxide (N O) for a time generally between 0.1 and 120 minutes.

Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition

A fabrication method for high voltage power devices with at least one deep edge ring includes the steps of growing a lightly doped N-type epitaxial layer on a heavily doped N-type substrate, growing an oxide on the upper portion of the epitaxial layer, masking and then implanting boron ions, etching the oxide to expose regions for aluminum ion implantation, forming a layer of preimplantation oxide, masking of the body regions with a layer of photosensitive material and implanting aluminum ions, and a single thermal diffusion process forming a layer of thermal oxide on the epitaxial layer and simultaneously forming at least one deep aluminum ring and an adjacent body region doped with boron.

Fabrication method for high voltage devices with at least one deep edge

Growing community of inventors

Catania, Italy

Cateno Marco Camalleri