Intel Corporation

Mellanox Technologies, Ltd.

Mellanox Technologies Denmark Aps

Casper Dietrich

Steen Bak Christensen

Barak Freedman

Henning Lysdal

Benny Christensen

Bjarke Goth

Eivind Johansen

Thorkild Franck

Amit Oren

Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. Some embodiments of the present invention may be directed to an electronic module that includes a multi-chip module (MCM) substrate having a first surface configured to be connected to a system printed circuit board and a second surface defining a central portion and a peripheral portion. The electronic module may include a main die positioned on the central portion of the second surface of the MCM substrate and in electrical communication with electrical traces of the MCM substrate. The electronic module may include MCM sockets positioned on the peripheral portion of the MCM substrate, where each MCM socket is configured to engage and support a mezzanine package substrate such that a main portion of the mezzanine package substrate extends beyond the peripheral portion of the MCM substrate.

Electronic modules for co-packaged optics and copper packages

A laser module includes one or more connectors and a laser source. The one or more connectors are configured to receive electrical power from, and to output a light beam to, a panel of a system. The laser source is configured to (i) be powered by the electrical power, and (ii) produce the light beam using the electrical power. The one or more connectors and the laser source are detachable from the panel, and when detached from the panel, the laser source is not powered by the electrical power.

Pluggable laser module with improved safety

A re-timer system that may include a phase recoverer ('PR'), first-in-first-out device ('FIFO') and retime clock multiplication unit (&#x201c;CMU&#x201d;). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Techniques to reduce transmitted jitter

A signal regenerator that reduces noise in a reference clock signal. In one possible implementation, phase comparisons between the reference clock signal and an input signal are made. Based on the phase comparisons, phases of a clock signal having a lower frequency than the reference clock signal are adjusted. Phases of the phase adjusted lower frequency clock signal are compared with phases of a divided down version of the reference clock signal. Based on such comparisons, phases of the reference clock signal may be adjusted.

Techniques to regenerate a signal

Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region. In an implementation, an indication may be provided when a transition of an input signal occurs within the desired transition region and an indication may be provided when a transition of an input signal occurs outside the desired transition reagion. In an implementation, a difference between a number of times when input signal transitions occur inside and outside of the desired transition region may be provided. Accordingly, a receiver of the input signal may decide whether to ignore or use the input signal based on the difference between a number of times when input signal transitions occur inside and outside of the desired transition region.

Techniques to monitor transition density of an input signal

Techniques to adjust sampling times of an input signal. The techniques may utilize multi-level modification of the phase of a sampling clock. For example, the level of modification of the phase of the sampling clock may depend on the phase angle of the sampling clock in which transitions of the input signal occur.

Techniques to adjust a signal sampling point

A lock detection method for generating a lock signal including providing a data signal and a clock signal to a clock detection unit, the data signal being describable by an eye pattern, the data signal and the clock signal being in lock when a data transition occurs in the center of a first transition period. A lock detection unit including: detection of absence or presence of a data transition of the data signal in a first partial period centered around the center of the first transition period and generating a first output signal having a first logic value in response to the presence of a data transition and having a second logic value in response to the absence of a data transition in the first partial period, detection of absence or presence of a data transition of the data signal in a second partial period centered around the center of the eye and generating a second output signal having a first logic value in response to the absence of a data transition and having a second logic value in response to the presence of a data transition in the second partial period, and comparing the first and second output signals and generating a lock signal according to the comparison.

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Roskilde, Denmark

Casper Dietrich