International Business Machines Corporation

Casper A Scalzi

Kenneth E Plambeck

Richard J Schmalz

Bhaskar Sinha

Richard I Baum

Glen A Brent

Carl Edward Clark

Michael Gerard Mall

William John Starke

Thomas J Dewkett

Terry L Borden

Steven Jay Greenspan

Alan G Ganek

Peter H Gum

James Lum

Justin R Butwell

Eric M Schwarz

Moon Jung Kim

David Bruce Lindquist

Leslie W Wyman

Richard P Tarcza

Douglas W Westcott

Eugene P Hefferon

Roger E Hough

Donald W McCauley

Francis E Johnson

James R Urquhart

John Fenton Scanlon

Harry M Yudenfriend

Mark S Farrell

Balakrishna Raghavendra Iyer

Jeffrey Alan Frey

Satya Prakash Sharma

Inderpal Singh Narang

Geoffrey Owen Blandy

Frank William Brice

Allan Samuel Meritt

Thomas Edward Cook

Joseph C Elliott

Brent Allen Carlson

Ronald M Smith

Donald Fred Ault

David B Emmes

Catherine Krueger Eilert

Kathryn Marie Jackson

Joseph M Gdaniec

Lee Hardy Wilson

Donald H Gibson

Frank W Brice

Julian Thomas

Alan I Alpert

Richard R Guyette

Ronald F Hill

Glenn W Sears, Jr

Joseph A Williams

David Richard Page

James G Brenza

Kenneth G Rubsam

Eugene S Schulze

John C Rathjen, Jr

James C Mazurowski

Gururaj Seshagiri Rao

Hatem Mohamed Ghafir

James J Antognini

Michel Henri Hack

Gururaj S Rao

George H Bean

Mark M Maccabee

Norman C Chou

Richard J Schmalz, Deceased

Stephen R Newson

Eddie T Hall

Mark E Rakhmilevich

Carol E Clark

Kenneth R Veraska

Christine R Panner

Donald W Mccauley

John C Rathjen

John F Scanlon

Hatem M Ghafir

Lee H Wilson

This invention describes a method and system for virtualizing an internal capability of a computing system; specifically, the invention describes a method and system for establishing a virtual machine containing a programmed hardware-machine function that is normally executed natively as proprietary internal code in its own hardware environment, a Central Electronics Complex (CEC) or logical partition of a CEC. The code resides in a separate hardware domain of the CEC called the Service Element (SE). The IBM VM/ESA (VM) operating system requests the SE to transfer a copy of the code into a virtual machine that VM has initialized, where the machine function is provided (in the current embodiment) as an isolated and encapsulated part of a virtual Parallel Sysplex system comprising multiple virtual CECs in a testing environment.

Method and system for providing a hardware machine function in a protected virtual machine

Six instructions for the manipulation of discontinuous memory locations in a computer memory are described. They are: Compare and Load (CL), Compare and Swap (CS), Double Compare and Swap (DCS), Compare and Swap and Store (CSST), Compare and Swap and Double Store (CSDST), and Compare and Swap and Triple Store (CSTST). In each instruction a processor associates a programming-specified blocking symbol with a lock not accessible to software. The lock is used by any of these instructions only during its single instance of instruction execution, and the lock is made available (unlocked) at the end of each instance to then enable another blocking-symbol instruction instance to use the lock, thereby serializing concurrent multiple processor requests for accessing the same resource. Programming associates resources in a system with the unique blocking symbols. Each instance of these instructions executes an operand earlier prepared from a data value taken from the resource.. The data value is checked for change during the instance of execution when equality indicates no change since its preparation. These blocking-symbol instructions significantly increase the computer's speed of changing noncontiguous locations in a resource, compared to the time needed by software-protocol locks which must operate over a plurality of instances to make corresponding changes in a resource.

Method utilizing a set of blocking-symbol resource-manipulation

Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

Preprocessing of stored target routines for controlling emulation of

Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture. Target routines (corresponding to the incompatible instruction instances in an incompatible program being emulated) are accessed, patched where necessary, and executed by a target processor to enable the target processor to precisely obtain the execution results of the emulated incompatible program. Before preprocessing, each target routine may not be able to provide identical execution results as required by the incompatible architecture, and the preprocessing may patch one or more of its target instructions to enable the target routine to perform the identical emulation execution of the corresponding incompatible instruction. The patching and other modifications to a target routine are done by one or more preprocessing instructions stored in the target routine.

Preprocessing of stored target routines for emulating incompatible

A method and apparatus for fully restoring the context of a user program, including program status word (PSW) and CPU register contents, following an asynchronous interrupt. Upon the occurrence of an asynchronous interrupt event, control is transferred from the normally executing part of the user program to an interrupt handler of the operating system kernel. The kernel interrupt handler saves the contents of the CPU registers and PSW as they existed at the time of the interrupt in a save area associated with the user program before transferring control to a signal catcher routine of the user program. When it has finished handling the interrupt, the signal catcher routine restores the previous state of program execution as it existed before the interrupt by storing the address of the save area in a selected register (which may be a general register/access register pair), restoring the contents of the registers other than the selected register containing the address of the save area, and then restoring the contents of the PSW and selected register by using a new Resume Program (RP) instruction. The RP instruction contains an operand field specifying through the selected register the base address of the save area together with offset fields specifying the offsets of the saved contents of the PSW and selected register relative to the beginning of the save area. Upon decoding an RP instruction, the CPU executing the instruction adds the displacement to the base address contained in the specified register to form the beginning address of the save area, to which it adds the specified offsets to access the saved PSW and selected register contents. The current PSW and selected register contents are then restored with the saved contents to fully restore the previous program context and return control to the instruction being executed at the point of interrupt. To ensure system integrity, only those fields of the PSW are restored that could have otherwise been restored by a program operating in problem state.

Method and apparatus for fully restoring a program context following an

Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses. After the processor has successfully written all of these addresses and associated operand data values into its PLO save area, the processor sets its RI indicator to the RI state, and then stores into the resource unit the data values stored in its PLO save area at the resource addresses also stored in its PLO save area, according to the FC also stored therein. After completing all changes in the resource, the processor sets its RI indicator to the non-RI (resource consistent) state. If the processor should ever fail while executing a PLO instance, it signals its failing condition to the system. Then, a RCR method is executed by any operational processor (acting as a RCR processor) to recover the consistency of the resource unit. The RCR method uses the state of the RI indicator with the failed processor's PLO save area, the FC stored therewith, and the content of the failed processor's PLO save area to restore the consistency of the resource unit.

Method of executing perform locked operation instructions for supporting

Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol field (called herein a PLT, program lock token, field), a lock field H, and a wait field W which is used to chain plural CLEs currently having the same blocking symbol. When the lock field H is set to a lock held state, it indicates the associated processor has exclusive rights to access a data resource unit associated with the blocking symbol in the CLE entry. When the wait field in a lock entry contains a pointer to another lock entry and the H field in the lock entry indicates a not held state, the associated processor is waiting for the resource and cannot further execute its PLO instance until it later gets set to the lock state, which is done by the processor of the prior CLE in the chain when it completes execution of its PLO instance. Each PLO instruction also has operand fields, and a function code (FC). The FC controls the manner of processing done by the PLO instance on its operands. Blocking symbols are specified by software to enable the software to utilize hardware enforced serialization of multi-processor accesses simultaneously requested for accessing the same data resource in the computer system. The plural processors may simultaneously, and at any time, initiate PLO instances for the same or different blocking symbols. When different processors simultaneously execute PLO instances having different blocking symbols, the processors may execute in parallel without conflict. But if the different processors simultaneously execute PLO instances having the same blocking symbol, the processors cannot execute in parallel without potential conflict, and the processors must serialize the execution of their PLO instances for accessing the same resource. In the latter case, their CLEs are chained through pointers in wait fields of the CLEs.

Processor associated blocking symbol controls for serializing the

PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol. The blocking symbol controls the PLO operations by serializing simultaneously PLO instruction access requests being made by multiple processors to the same resource unit using the same blocking symbol to allow only one PLO instruction instance to have exclusive access to the resource at a time.

Blocking symbol control in a computer system to serialize accessing a

A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.

Coexecution processor isolation using an isolation process or having

A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses 'source effective addresses' (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).

Storage access authorization controls in a computer system using dynamic

A method of utilizing large virtual addressing in a target computer to implement an instruction set translator (1ST) for dynamically translating the machine language instructions of an alien source computer into a set of functionally equivalent target computer machine language instructions, providing in the target machine, an execution environment for source machine operating systems, application subsystems, and applications. The target system provides a unique pointer table in target virtual address space that connects each source program instruction in the multiple source virtual address spaces to a target instruction translation which emulates the function of that source instruction in the target system. The target system efficiently stores the translated executable source programs by actually storing only one copy of any source program, regardless of the number of source address spaces in which the source program exists. The target system efficiently manages dynamic changes in the source machine storage, accommodating the nature of a preemptive, multitasking source operating system. The target system preserves the security and data integrity for the source programs on a par with their security and data integrity obtainable when executing in source processors (i.e. having the source architecture as their native architecture). The target computer execution maintains source-architected logical separations between programs and data executing in different source address spaces--without a need for the target system to be aware of the source virtual address spaces.

Method of using a target processor to execute programs of a source

A control process which enables a non-supervisory 'using program' (e.g. application programs) to directly interface one or more shared asynchronous hardware facilities in a computer system. Any using program may request the operating system (OS) to set up a 'special environment' with an AHF during which the using program can directly issue requests to the AHF for its services. The OS sets up a session for the using program having the 'special environment', which specifies restrictions on storage accesses by the AHF for accesses made on behalf of the using program--to insure system data integrity. These restrictions are not changeable by the using program. The 'special environment' exists until the session is ended by the using program or by a terminating condition. The 'special environment' is tailored to be different among the different using program concurrently using the same AHF, so that the 'special environment' of one using program cannot interfere with the 'special environment' of another using program. During a session, work requests for any using program are communicated directly to the AHF from the using program, and completion of any work request is communicated directly by the AHF to the using program without any interruption of the using program or OS involvement.

Interface control process between using programs and shared hardware

Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) from central processing units of a data processing system which specify data move requirements of the data processing system. QEs can be transferred between queues of other DMPs or a common queue to achieve load balancing, recovery and reconfiguration control.

Load balancing, error recovery, and reconfiguration control in a data

Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.

Dynamic program analyzer facility

Growing community of inventors

Poughkeepsie, NY, United States of America

Casper A Scalzi