Synopsys, Inc.

Casey The

Jovanka Ciric Vujkovic

Patrick Vuillod

Luca Gaetano Amaru

Jiong Luo

Peter Moceyunas

A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

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Cupertino, CA, United States of America

Casey The