Astera Labs, Inc.

Texas Instruments Corporation

Asiera Labs, Inc.

Casey Morrison

Pulkit Khandelwal

Ken (Keqin) Han

Enrique Musoll

Subbarao Arumilli

Vikas Khandelwal

Charan Enugala

Jitendra Mohan

Vivek Trivedi

Chi Feng

Pakyiu Leung

Lee Martin Sledjeski

A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Retimer with path-coordinated flow-rate compensation

An integrated-circuit retimer selectively logs information corresponding to mission-mode data, received and transmitted via counterpart high-bandwidth data interfaces, in real-time and accordance with contents of a logging control storage written by an external component during retimer run time.

Retimer with host-interactive data logging engine

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Low-latency retimer with seamless clock switchover

A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Low-latency signaling-link retimer

First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

Retimer with mesochronous intra-lane path controllers

Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Configurable-aggregation retimer with media-dedicated controllers

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

Semiconductor package with terminal pattern for increased channel density

Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.

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San Jose, CA, United States of America

Casey Morrison