Integrated Device Technology, Inc.

Esco Group LLC

Casey E Springer

Tak Kwong Wong

Yunsheng Wang

Bill Beane

Michael R Weeks

Kyle J Meeuwsen

Jiann-Jeng (John) Duh

Tzong-Kwang (Henry) Yeh

Discharge grate components for reducing machines including stops to inhibit pokers within the grate so that the pokers are not ejected from the grate with a high velocity.

Discharge grates for reduction mills

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.

Systems and methods for monitoring and controlling binary state devices using a memory device

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.

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Portland, OR, United States of America

Casey E Springer