Hewlett-Packard Company

Casey D Hoekstra

Richard I Klaus

Thomas B Pritchard

Douglas L Franz

Digital integrated circuit testable input/output pad logic includes modified output driver logic and a latch for storing a test bit provided externally at the I/O pad terminal. The output driver logic selects either the normal pad output signal (O) for output during normal operation, or the stored test bit (S) or its complement (S') for output during a test operation. The output driver logic and latch are controlled by control logic signals (DP,SP,NDN,LS,NLS,NSN) derived from common tri-state (NTR) and latch (NTM) test signals provided externally at dedicated test pins (NTR,NTM). The control logic signals are provided over a bus to all similar testable I/O pads for testing all testable I/O pads within the IC under control of the two test signals.

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Corvallis, OR, United States of America

Casey D Hoekstra