Nxp B.v.

Cas Groot

Rinze Meijer

Jose De Jesus Pineda De Gyvez

Rinze Ida Mechtildis Peter Meijer

Maurits Storms

Marco Lammers

Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.

Method and system for fast initialization of a memory unit

A power selector for switching power supplies is implemented using a variety of methods and devices. According to an example embodiment of the present disclosure, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The first power circuit provides a regulated level of power to the integrated circuit (IC) having an operating power level specified as a circuit operating level for providing power to the IC. The second power circuit provides power to the IC. A power-signal arbitration circuit for assessing Vand whether the second power circuit is to provide power to the IC as an alternative to the first power circuit providing power to the IC is based on a threshold power level indicative of the specified operating power level and the regulated level of power. Based on the power-signal arbitration circuit's assessment, providing an arbitration-control signal to the power-signal switching circuit.

Power arbitration method and apparatus having a control logic circuit for assessing and selecting power supplies

Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.

Power-switch test apparatus and method

Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed.

Adjustable body bias circuit

A method of designing a power switch block () for an integrated circuit layout in a predefined integrated circuit technology is disclosed. The power switch block () includes a segment () comprising a plurality of spaced parallel conductors () each having a predefined height in said technology, a stack of a first power switch () of a first conductivity type and a pair of drivers () for respectively driving the first power switch () and a second power switch (), said drivers having predefined dimensions in said technology, and the second switch () of a second conductivity type. The method comprises providing respective predefined width/length ratios for said power switches (); determining a total height of the segment () from the sum of the predefined heights of the individual conductors () and respective spacings () between said individual conductors, determining the height of the first transistor () from the difference between the total height and the predefined driver height; determining the width of the first transistor () from the combined predefined widths of the pair of drivers (); optimizing the first power switch layout within its determined height and width based on its predefined width/length ratio; and optimizing the second power switch layout based on its predefined width/height ratio.

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Antwerp, Belgium

Cas Groot