Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Carsten Stoerk

Stefan Reithmaier

Eduardas Jodka

Julian Becker

Josy Bernard

Nicolas M Guibourg

Joerg Kirchner

Ruediger Ganz

Johann Erich Bayer

Juha S Timonen

Florian Neveu

Damian Panter

Stefan A Reithmaier

In an example, a method includes enabling a first voltage supply and a second voltage supply. The method also includes selecting, with a decision comparator, a selected voltage supply from either the first voltage supply or the second voltage supply based on which of the first voltage supply or the second voltage supply ramps up first. The method includes monitoring the selected voltage supply with the decision comparator. The method also includes, responsive to a voltage from the selected voltage supply dropping below a dropout voltage level of a low dropout regulator, switching to an other voltage supply with the decision comparator.

Supply selection circuit with input noise suppression and wide operating range

Systems, methods, and circuitries are provided for generating an acceleration current in response to a threshold temperature being reached. In one example, temperature based acceleration current source circuitry includes a first temperature sensitive device, a second temperature sensitive device, differential trigger circuitry, and an acceleration current source. The first temperature sensitive device is configured to generate a first signal that varies responsive to temperature changes at a first rate. The second temperature sensitive device is configured to generate a second signal that varies responsive to temperature changes at a second rate. The differential trigger circuitry is configured to generate a trigger signal based on a difference between the first signal and the second signal. The acceleration current source circuitry is configured to output an acceleration current in response to the trigger signal.

Temperature dependent acceleration current source circuitry

A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Process of operating switched-mode DC/DC converter having a bootstrapped high-side driver

An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.

Glitch reduction in segmented resistor ladder DAC

Switched-mode DC/DC converter having a bootstrapped high-side driver

A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.

Self-biased gate controlled switching circuit

A circuit includes a digital-to-analog converter (DAC) having a DAC input and a DAC output. The circuit includes a reference voltage (VREF) generator having a VREF generator input, a VREF generator output, and a VREF power supply input. The VREF generator output is coupled to the DAC input. A voltage regulator has a voltage regulator input and a voltage regulator output. The voltage regulator output is coupled to the DAC. A clamp circuit has a first clamp circuit input, a second clamp circuit input, and a clamp circuit output. The first clamp circuit input is coupled to the voltage regulator input, and the clamp circuit output is coupled to the VREF power supply input. The second clamp circuit input is coupled to the voltage regulator output. The clamp circuit includes a source-follower circuit having the second clamp circuit input.

Supply voltage clamping for improved power supply rejection ratio

A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching

An electronic device comprising a level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain, the level shifter having a high-side transistor in series with a low-side transistor so as to provide an output node between the channel of the high-side transistor and the channel of the low-side transistor for driving a load with the high level output signal of the second voltage domain. The level shifter being configured to have a first state in which the high-side transistor is conducting and the low-side transistor is not conducting, a second state in which the low-side transistor is conducting and the high-side transistor is not conducting and a third state in which the high-side transistor is not conducting and the low-side transistor is not conducting.

Electronic device with gate driver for high voltage level shifter

Conventional current sharing circuits, which can be used in drivers for liquid crystal displays (LCDs), for example, often use bipolar transistors. However, bipolar transistors are not available in many CMOS processes. Thus, a current sharing circuit is provided here that employs CMOS transistors. In particular, the circuit provided here uses a current mirror and pass circuit to assist in providing this current sharing function.

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Freising, Germany

Carsten Stoerk