Infineon Technologies Ag

Carsten Schäffer

Hans-Joachim Schulze

Anton Mauder

Franz-Josef Niedernostheide

Holger Schulze

Frank Hille

Manfred Pfaffenlehner

Franz Hirler

Thorsten Meyer

Armin Willmeroth

Uwe Wahl

Markus Schmitt

Carolin Tolksdorf

Oliver Humbel

Mathias Plappert

Angelika Koprowski

Michael Rüb

A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.

Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof

A lateral trench transistor has a semiconductor body having a source region, a source contact, a body region, a drain region, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded. A heavily doped semiconductor region is provided within the body region or adjacent to it, and is electrically connected to the source contact, and whose dopant type corresponds to that of the body region.

Lateral trench transistor, as well as a method for its production

A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

Semiconductor device and fabrication method

A semiconductor device according to the invention has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

Semiconductor device and fabrication method suitable therefor

Transistor cells () of a power transistor component are in each case provided with a gate conductor structure that forms a gate electrode () in sections and is connected via a gate cell terminal () to a gate wiring line () led to a gate terminal () of the power transistor component (). The gate conductor structure () has a desired fusible section () with an increased resistance, which is arranged within a cavity. The resistance of the desired fusible section () can be set in such a way that, in the event of a current loading of the magnitude of a value that is typical of a defective gate dielectric (), the gate conductor section () is interrupted in the desired fusible section () and the gate electrode () is disconnected from the gate wiring line (). The power transistor component can be produced with high yield and has a smaller number of failures during application operation.

Power transistor cell and power transistor component with fusible link

Growing community of inventors

Sattendorf, Austria

Carsten Schäffer