International Business Machines Corporation

Carsten Otte

Christoph Raisch

Marco Kraemer

Matthias Klein

Jonathan D Bradbury

David F Craddock

Michael F Fee

Ulrich Weigand

Christian Borntraeger

Ralf Winkelmann

Edward W Chencinski

Jens Mehler

Hanno Eichelberger

Jakob Christopher Lang

Martin Schwidefsky

Stefan Roscher

Joachim Von Buttlar

Hoang-Nam Nguyen

Matteo Michel

Stefan Usenbinz

Christoph Vincent Schlameuss

Florian Merkert

Christian Ehrhardt

Georg Drache

Sebastian Stork

Oleg Tsemaylo

Christopher Noelting

Matthias Brachmann

Jana Christine Aberham

An approach for generating a compiled version of a program source code. At least two different executable files may be generated applying at least two different compiler optimization settings for compiling a first part and applying at least two different compiler optimization settings for compiling a second part of the source code. A main performance part of the source code may be determined dependent on values of a target quantity of the at least two different executable files. The main performance part is the part of the first part and the second part that has a greater influence on the target quantity. The compiled version of the program source code may be generated by compiling the source code applying a higher optimization level of the compiler for compiling the main performance part than for compiling the remaining part of the source code.

Generating debuggable executables based on optimizing different compiler options for source code modules

The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

A computer-implemented method for simulating a system of at least two computing systems connected via at least one data packet connection, wherein a computing system comprises interconnect adapters for physical connections based on a physical layer protocol each. A packet switching component is provided, as are physical attachments for each interconnect adapter. The physical attachments are registered. A connection director is provided for managing the data packet exchange. In response to the receipt of a simulation start indicator, each physical attachment registers its unique address at the package switching component. This assigns unique identifiers for each computing system, and unique identifiers for simulated physical layer protocols.

Simulating a system of computing systems

The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Executing an atomic primitive in a multi-core processor system

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

MMIO addressing using a translation lookaside buffer

Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.

Thermal capacity optimization for maximized single core performance

A cloud computing system includes a virtual server outputs non-encrypted data and receives encrypted data in response to receiving a write request signal and a read request signal. A hosting server hypervisor receives the write request signal and the read request signal. In response to receiving the write request signal the hosting server hypervisor writes encrypted data corresponding to the write request signal into a storage device. In response to receiving the read request signal the hosting server hypervisor obtains encrypted data corresponding to a data read request signal from the storage device and outputs the encrypted data. A secure channel sub-system is installed between the at least one virtual server and the hosting server hypervisor. The secure channel sub-system stores a virtual device key in a key storage unit and prevents the virtual server and the hosting server hypervisor from accessing the key

I/O encryption device protected against malicious hypervisors

Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Asymmetric storage data distribution

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

MMIO addressing using a translation table

An aspect includes a computer system with a network encryption device and a trusted container within firmware or hardware and/or within a virtual machine running on the computer system. The network encryption device includes a key store for storing secret encryption keys and a network traffic encryption engine for negotiating and/or storing encryption keys in the key store and/or for encrypting and/or decrypting network traffic using the encryption keys from the key store. The trusted container includes a flow analyzer for analyzing network traffic received from the network encryption device.

Encryption with sealed keys

The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.

Memory access based I/O operations

Updating a database is provided. The updating is noticeable by all read and/or write processes. In response to a write request to the database, a temporary copy of the database is generated. The write operations are performed to the temporary copy of the database. The current database generation of the database is replaced with the temporary copy for creating a next database generation.

Updating a database

A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

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Stuttgart, Germany

Carsten Otte