Infineon Technologies Ag

Carsten Ohlhoff

Peter Beer

Jochen Hoffmann

Helmut Schneider

Peter P&ouml;chm&uuml;ller

Hans-Christoph Ostendorf

Stefan Gollmer

In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.

Test apparatus and method for testing a circuit unit

Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

Method and apparatus for masking known fails during memory tests readouts

The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Memory module, test system and method for testing one or a plurality of memory modules

A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Test circuit and method for testing an integrated memory circuit

A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data generator has a shift register.

Data generator for generating test data for word-oriented semiconductor memories

A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

Test device, test system and method for testing a memory circuit

The invention relates to a dynamic memory having a memory cell array, a test controller to test the memory cell array and an oscillator to control the refreshing of the memory cell array. According to the invention, the memory includes a device for using the oscillator as a time base for the test controller, such that a slow time base is achieved which may be used for different self-tests of the memory.

Dynamic memory and method for testing a dynamic memory

To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.

Integrated semiconductor circuit configuration

The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The current measuring unit is connected to an output device in order to output the value of the measured current to an external test system via an external connection of the integrated circuit.

Integrated circuit having a current measuring unit

A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

Memory module with improved electrical properties

A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Semiconductor chip with trimmable oscillator

A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

Testing device for testing a memory

The invention relates to a configuration for the measurement of internal voltages in a DUT ( ), in which a comparator ( ) is provided in each DUT ( ) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).

Configuration for measurement of internal voltages of an integrated semiconductor apparatus

The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.

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München, Germany

Carsten Ohlhoff