Robert Boschgmbh

Carsten Hermann

Ralph Bauer

Matthias Beckert

Lothar Jakobi

Martin Kaiser

Johannes Kunst

Christoph Land

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

Integrated circuit and method for limiting a switchable load current

An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.

Electrical circuit for testing primary internal signals of an ASIC

An electrical circuit for ensuring safe ramp-up and ramp-down of at least a regulated operating voltage, a reference voltage, and a reset signal for a consumer is described. The electrical circuit includes a voltage reference circuit and a voltage regulator. The voltage regulator is provided in order to furnish a regulated operating voltage, the voltage reference circuit is provided in order to be supplied with the regulated operating voltage furnished by the voltage regulator, and the voltage regulator is provided in order to obtain a reference voltage from the voltage reference circuit.

Electric circuit for the safe ramp-up and ramp-down of a consumer

A voltage reference circuit serves to furnish a reference voltage for an application-specific integrated circuit. The voltage reference circuit includes a voltage input for applying an operating voltage; a ground terminal; a voltage output for furnishing a reference voltage; and a signal output for furnishing a power-on reset signal. The voltage reference circuit includes an IPTAT circuit, connected between the voltage input and ground terminal, for generating a current proportional to the absolute temperature, the voltage reference circuit being embodied to furnish the power-on reset signal only if the reference voltage has reached a target value and if additionally a current is flowing in the IPTAT circuit with a quantity of current that reaches or exceeds a minimum current intensity determined by a voltage value of the operating voltage and by a pull-down resistance value.

Voltage reference circuit with combined power-on reset

A circuit for pulse duty factor limitation in a switch mode regulator, having an output stage to which control is applied by a signal, is described, in which circuit a pulse duty factor limiter is connected to the switch mode regulator in order to transfer the signal to the pulse duty factor limiter; the pulse duty factor limiter is configured to generate from the signal a limited signal limited at the top end in terms of pulse duty factor; and the pulse duty factor limiter is connected to the output stage in order to transfer the limited signal to the output stage. Also proposed is a method for operating a switch mode regulator having a downstream circuit to which control is applied by a signal of the switch mode regulator and having a capacitor that becomes charged when the downstream circuit is switched off, in which method the pulse duty factor of the signal is limited at an upper limit value in such a way that a predetermined charging time for the capacitor is available.

Circuit for pulse duty factor limitation in a switch mode regulator, and method for operating a switch mode regulator

A circuit arrangement for activating a control device includes: a first switch in a main current path, via which the control device is activated; an alternative current path; and a control logic which compares a voltage present for activating the control device to a threshold voltage and opens the first switch if the threshold voltage falls below so that a higher volume of an interference current effectuated by the present negative voltage flows via the alternative current path.

Method for activating a control device

A circuit for generating an output signal having a second pulse duty factor from an input signal having a first pulse duty factor includes a first capacitor and a second capacitor which are each connected to a charge source for periodically charging the capacitors. A voltage across the charged first capacitor is defined as a reference voltage, and the pulse duty factor of the output signal is defined by the charging period of the second capacitor required for reaching the reference voltage.

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Reutlingen, Germany

Carsten Hermann