Advanced Micro Devices Corporation

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Carsten Hartig

Daniel Fischer

Alok Vaid

Gunter Grasshoff

Holger S Schuehrer

Christin Bartsch

Kai Frohberg

Thomas Werner

Matthias Schaller

Hartmut Ruelke

Paul Willard Ackmann

Christoph Schwan

Peter Moll

Martin Mazur

Gert Burbach

Bernd Schulz

Gotthard Jungnickel

Lokesh Subramany

Johannes Groschopf

Jason Phillip Cain

Matthias Ruhm

Guo Xiang Ning

Georg Sulzer

Frank Heinlein

Adam Michal Urbanowicz

Stefan Thierbach

Fanghong Gn

Stefan Rongen

Andreas Schuring

Guido Überreiter

Martin Schmidt

Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

Method for in-die overlay control using FEOL dummy fill layer

Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.

Systems and methods for fabricating semiconductor device structures

Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved.

Inline residual layer detection and characterization post via post etch using CD-SEM

A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.

Detection of particle contamination on wafers

A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Layout for reticle and wafer scanning electron microscope registration or overlay measurements

Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.

Systems and methods for fabricating semiconductor device structures using different metrology tools

A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

Incorporating film optical property measurements into scatterometry metrology

By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.

Method of reducing contamination by removing an interlayer dielectric from the substrate edge

By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer

Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.

Method of compensating for etch rate non-uniformities by ion implantation

By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer, an opening is formed by means of standard lithography and etch techniques and, subsequently, a spacer layer is conformally deposited, wherein a thickness of the spacer layer at the sidewalls of the opening substantially determines the effective width of the microstructure element to be formed. By using standard 193 nm lithography and etch processes, gate electrodes of 50 nm and beyond can be obtained without significant changes in standard process recipes.

Method of defining the dimensions of circuit elements by using spacer deposition techniques

In a system and a method for controlling critical dimensions of features to be formed on a substrate, a measurement device is coupled to an etch tool to form a feedback loop to control the critical dimensions on a wafer basis instead of a lot basis. In a further embodiment, the etch tool is in communication with a control unit that allows controlling of the etch tool and/or of the photolithography tool on the basis of an etch model. Thus, variations within a lot may be compensated by a software implementation of the etch model. The control unit may be implemented in the etch tool or an external device.

System and method for wafer-based controlled patterning of features with critical dimensions

A semiconductor device structure comprises a corner structure enclosed by a delineation region, wherein the shape of the corner structure does not exhibit any symmetry with respect to point symmetry and axial symmetry, such that the corner structure is unambiguously recognizable by an automated alignment system. Furthermore, the inner region of the corner structure may be filled with a pattern indicating the type of material layer in which the corner structure is formed. The corner structure exhibits a strong contrast even if the wafer is subjected to a CMP treatment.

Die corner alignment structure

A method comprises a &ldquo;two-step&rdquo; formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.

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Meerane, Germany

Carsten Hartig