Ncr Corporation

Carson T Schmidt

Timothy G Goldsbury

William P Ward

Robert O Gunderson

Rocky M Young

Jerrold L Allen

Barry L Loges

Gregory D Brinson

Jerry K Herreweyers

Chenyu Chao

A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory. The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.

Direct execution of software on microprogrammable hardware

An error detection and correction apparatus including a transmission bus for transmitting multi-bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code technique. Parity generators are connected to the bus for receiving the bits of the data signals and selected bits of the error correction code signals in accordance with the modified Hamming code technique for determining if a single bit error exists in the data. A two-state comparison gate is connected to the parity generators which has a first state if a single bit error does exist, and a second state if a single bit error does not exist. A separate error detection and correction circuit is provided to detect and correct any single bit errors in the data on the transmission bus. The two-state comparison gate is reset to its second state after the separate error detection and correction circuit corrects any single bit error in the data.

Error detection and correction system

A cache memory has a data buffer for storing blocks of data from a main memory and an index for storing main memory addresses associated with the data blocks in the data buffer. The size of the blocks of data stored in the data buffer can be varied in order to increase the 'hit ratio' of the cache memory. The index is a set associative memory and bits provided to an address input of the index are selectively inhibited by an address inhibit circuit when the size of the data blocks in the data buffer is to be varied. A block size register stores block size information that is provided to the address inhibit circuit. The block size information is also provided to a fetch generate counter and a fetch return counter that control the number of words transferred as a block from the main memory to the cache memory.

Cache memory having a variable data block size

A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.

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Poway, CA, United States of America

Carson T Schmidt