Analog Devices,inc.

Analog Devices International Unlimited Company

Carroll Clifton Speir

Eric Otte

Nevena Rakuljic

Jeffrey Paul Bray

Matthew Louis Courcy

Reuben Pascal Nelson

James C Camp

John Kevin Behel

Kenny Gentile

Matthew D McShea

Ahmed Mohamed Abdelatty Ali

Michael Ray Elliott

Scott Gregory Bardsley

Ravi Kishore Kummaraguntla

Ryan Lee Bunch

David H Robertson

Ralph David Moore, Jr

Siddharth Devarajan

Bryan Scott Puckett

Corey Petersen

Peter Delos

Joseph Bradford Brannon

William George John Schofield

Satishchandra G Rao

Vinoth Kumar

Bhanu Pande

Joseph Bradford Bannon

Scott Bradsley

Sajkapoor P K

Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.

Programmable digital loopback for RF applications

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Bi-directional interface for device feedback

A sample rate converter ('SRC') for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate ('F') and output from the SRC at an output rate (&#x201c;F&#x201d;) equal to F*L/M. The SRC includes a low pass filter (&#x201c;LPF&#x201d;) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tinput samples to the filter at a given time, wherein Tis a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tof the coefficients to the LPF at a given time.

Techniques for input formatting and coefficient selection for sample rate converter in parallel implementation scheme

A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or 'one shot' accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

Open loop oscillator time-to-digital conversion

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Signal path linearization

Phase control of clock signal based on feedback

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Microprocessor-assisted calibration for analog-to-digital converter

Randomly sampling reference ADC for calibration

Efficient calibration of errors in multi-stage analog-to-digital converter

Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Variable dynamic range receiver

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

Pipelined converter systems with enhanced linearity

An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.

Analog-to-digital converter with low latency output path

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Pleasant Garden, NC, United States of America

Carroll Clifton Speir