Lucent Technologies Inc.

Carolyn W Spivak

Satwant Singh

Barry K Britton

Richard G Stuby, Jr

Ho Trong Nguyen

Kai-Kit Ngai

Ian L McEwen

Gary P Powell

William B Andrews

The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.

Global signal distribution with reduced routing tracks in an FPGA

A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.

Programmable logic device with logic cells having a flexible input

The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic '1' output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic '0' output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.

Bi-directional buffers and supplemental logic and interconnect cells for

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Emmaus, PA, United States of America

Carolyn W Spivak