Motorola Corporation

Sandia Corporation

Freescale Semiconductor,inc.

Carole C Barron

Robert E Jones

Eric D Luckowski

Stephen Montague

Bradley M Melnick

James G Fleming

Dale L Hetherington

Yasuhito Shiho

A self-aligned magnetic clad bit line structure () for a magnetic memory element () and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure () extends within a trench () and includes a conductive material (), magnetic cladding sidewalls () and a magnetic cladding cap (). The magnetic cladding sidewalls () at least partially surround the conductive material () and the magnetic cladding cap () is substantially recessed within the trench with respect to the top of the trench.

Self-aligned magnetic clad write line and its method of formation

A self-aligned magnetic clad bit line structure ( ) for a magnetic memory element ( ) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure ( ) extends within a trench ( ) and includes a conductive material ( ), magnetic cladding sidewalls ( ) and a magnetic cladding cap ( ). The magnetic cladding sidewalls ( ) at least partially surround the conductive material ( ) and the magnetic cladding cap ( ) is substantially recessed within the trench with respect to the top of the trench.

A method for forming an embedded DRAM integrated circuit (,) begins by forming an asymmetric source and drain structure on the DRAM pass transistors. The asymmetric DRAM transistor structure has a lightly doped shallow current electrode (,) that connects to a trench capacitor (,and,). The bit line current electrode of the DRAM pass transistor is formed having an LDD region (,) and an adjacent highly doped drain region (,). The region (,) helped to improve DRAM data retention reliability. In addition, the current electrode connected to the bit line is silicided to form a silicide region (,) which has improved coupling to an overlying tungsten plug (,). In addition, a P-type halo implant (,) is used to reduce or eliminate adverse short channel effects within a DRAM device.

Method of forming embedded DRAM structure

A method is disclosed for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The MEM device can be fabricated within a substrate cavity and encapsulated with a sacrificial material. This allows the MEM device to be annealed and the substrate planarized prior to forming electronic circuitry on the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the electronic circuitry can be protected by a two-ply protection layer of titanium nitride (TiN) and tungsten (W) during an etch release process whereby the MEM device is released for operation by etching away a portion of a sacrificial material (e.g. silicon dioxide or a silicate glass) that encapsulates the MEM device. The etch release process is preferably performed using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCI) which reduces the time for releasing the MEM device compared to use of a buffered oxide etchant. After release of the MEM device, the TiN:W protection layer can be removed with a peroxide-based etchant without damaging the electronic circuitry.

Method for integrating microelectromechanical devices with electronic

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

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Austin, TX, United States of America

Carole C Barron