U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Carole A Fisher

David H Paxman

Philip H Bird

Nigel David Young

David J Coe

John R A Ayres

Stanley D Brotherton

Frnak W Rohlfing

Reginald C Oldfield

A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer ( ) is etched back underneath a mask layer ( ). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam ( ).

Electronic device manufacture

A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity type.

High voltage lateral enhancement IGFET

A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

Method of manufacturing lateral IGFETS including reduced surface field

A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thin region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer. A window (26) is opened in the conductive layer on the relatively thick region of the insulating layer and the insulating layer is then etched isotropically through the window in the conductive layer to form a window (25) in the relatively thick region of the insulating layer thereby leaving part (29) of the conductive layer overhanging the edge of the window in the insulating layer. The conductive layer is then selectively etched with at least the area of the conductive layer spaced from the window masked so as to remove the part (29) overhanging the edge of the window (25) in the insulating layer. Impurities are then introduced using the insulated gate structure (12) as a part of a mask to form a source region (9) aligned with the insulated gate and a drain region (10) aligned with the window in the conductive layer (15, 16).

Method of manufacturing an insulated gate field effect transistor

A bipolar semiconductor device with interdigitated emitter and base regions has a sub-region of the base, which has a shorter carrier recombination time than the major part of the base region due to the presence of argon ion implantation induced carrier recombination centers. The sub-region of the base is located centrally with respect to the emitter region to intercept the transient current lines during device turn-off and so to promote collapse of the transient current and the avoidance of second breakdown of the device. The centrally located sub-region of the base is remote from the emitter region edges to collector region current flow when the device is on. The ions may be implanted at energies between 50 keV and 3 MeV and at doses between 10.sup.11 ions cm.sup.-2 and 10.sup.14 ions cm.sup.-2. The implanatation mask may be provided by photolithographically processed resist having a thickness between 0.5 .mu.m and 4 .mu.m dependant on the ion implantation energy. The depth of the sub region and the concentration of recombination centers within the sub-region may be varied by altering the implantation conditions to tailor the effect of the sub-region to the likelihood of the onset of second breakdown at any part of a device structure. The invention is particularly of use in transistors, and in thyristors.

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Horley, United Kingdom

Carole A Fisher