Sandia Corporation

Other

Carol I H Ashby

Hong Q Hou

Albert G Baca

Nein-Yi Li

Carolyn M Matzke

Ping-Chih Chang

Leonardo Griego

An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V , thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Npn double heterostructure bipolar transistor with ingaasn base region

A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.

Formation of interconnections to microfluidic devices

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Stable surface passivation process for compound semiconductors

Growing community of inventors

Edgewood, NM, United States of America

Carol I H Ashby