Northern Telecom Limited

Carmine A Ciancibello

Ernst A Munter

Youssef A Geadah

Martin C Lefebvre

Dennis W Mitchler

A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily 'hold' the output from the counters. This enables the counters to be re-loaded with their original 'count' to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Comparators and logic circuitry are used to provide two status output signals, namely full (or not) and empty (or not).

Message FIFO buffer controller

A time compression multiplex digital transmission system having an improved frame synchronization circuit in which a limited window is gated open at a master station to search for the final synchronization bit of the incoming burst signal from a slave station. Thereafter the window is expanded to open just prior to the anticipated arrival of the initial synchronization bit of the following burst. Once the presence of this initial synchronization bit is confirmed frame synchronization of the incoming burst signal is established and the window is then gated substantially coextensively with that incoming signal.

Frame synchronization circuit for digital transmission system

A digital conference circuit for a digital telephone switching network is provided, connected between a receive TDM (time division multiplex) bus carrying PCM (pulse code modulation) words from the conferees to the conference circuit and a transmit TDM bus carrying PCM words from the conference circuit to the conferees. For a conference involving N conferees, N-1 shift registers serially interconnected are employed. As each PCM word, in a distinct time slot on the receive TDM bus, reaches the conference circuit it is entered into the first shift register in the series. The PCM words already stored in the shift registers are 'shifted' along the series connection of shift registers by one register each time a new PCM word is entered in the first register, with the PCM word previously stored in the final shift register simply being 'lost.' Circuitry within the conference circuit monitors the binary value of the PCM words stored in the registers and during the time slot that one PCM word is being received from a conferee, the PCM word previously stored in one of the N-1 registers that has the largest absolute binary value is output on the transmit TDM bus and it is received by the conferee who is 'talking' during that same time slot (referenced to the conference circuit). With such a conference circuit a conferee never hears himself since the selection of whom he shall hear is made from the PCM words of all the other (i.e. N-1) conferees.

Digital conference circuit

A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produced. The twenty-four bit product can be coded as an unsigned seven-bit binary number (.mu.-255 code) as follows. The number 33.times.2.sup.11 in binary form is added to the linear product to form an augmented product. The number of leading zeroes in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are used for the four least significant bit positions of the coded product. Suitable circuitry is described which allows the coding process, just described, to take place while the linear product is in the process of being formed, and produces the coded result when the final linear product is completed.

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Carmine A Ciancibello