Stmicroelectronics S.r.l.

Carmelo Ucciardello

Antonino Conte

Giovanni Matranga

Gaetano Palumbo

Domenico Pappalardo

Mario Micciche

Santi Nunzio Antonino Pagano

Gianbattista Logiudice

Alfredo Signorello

Rosario Roberto Grasso

FrancescoNino Mammoliti

Diego De Costantini

Francesco Sorrentino

De Costantini Diego

Paolo Scalisi

Giuseppe Maganuco

Rosa Di Mauro

Carmine D'Alessandro

Mario Micchche'

Santi Pagano

A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal.

DC-DC down-converter with time constant comparison regulation system

A voltage regulator has an input terminal for receiving a supply voltage and an output terminal for providing a regulated voltage and a regulated current. Furthermore, the voltage regulator includes a regulator for generating the regulated voltage and the regulated current according to a regulation of the supply voltage. The regulator includes a plurality of regulation branches arranged between the input terminal and the output terminal, each one for providing an output voltage used for obtaining the regulated voltage and for providing an output current contributing to define the regulated current. The regulation branches are partitioned into a plurality of subsets each one including components adapted to operate within a corresponding maximum voltage different from the maximum voltage of the other subsets. In addition, the regulator includes a selector for selectively enabling the regulation branches according to an indicator of the supply voltage.

Voltage regulator for contact-less electronic devices

A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Dynamic biasing circuit for a protection stage using low voltage transistors

A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals.

Level-shifter circuit using low-voltage transistors

The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages.

Charge pump circuit using low voltage transistors

A charge pump including first and a second charge-pump stages electrically coupled, four pump capacitors connected between two enable terminals and four internal nodes, two pump transistors connected to the pump capacitors and to the internal nodes, and having respective control terminals, two biasing capacitors, connected between the control terminals and the enable terminals, and an equalization circuit connected between the control terminals and structured to limit the voltage between the control terminals within a first range of values.

Latch charge pump with equalization circuit

A charge pump latch circuit is provided that includes at least one first and at least one second charge pump stage interconnected by an intermediate circuit node, and a stabilization stage connected to the intermediate circuit node and to control terminals of transistors of the first and second charge pump stages. The stabilization stage includes at least one first pair and at least one second pair of first and second enable terminals receiving suitable and distinct phase signals that ensure the turn-off of the stabilization stage during overlapping periods of the phase signals. Also provided is a method for using a stabilization stage to drive transistors in first and second charge pump stages that are interconnected by an intermediate circuit node.

Electronic circuit for generating low voltage and high frequency phases in a charge pump

An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.

Biasing circuit for EEPROM memories with shared latches

A latch-type charge pump circuit is provided having first and second charge pump stages interconnected by an intermediate circuit node. The charge pump circuit includes first pump capacitors respectively coupled between first and second enable terminals and respective first inner circuit nodes, second pump capacitors respectively coupled between the second and first enable terminals and respective second inner circuit nodes, latch transistors coupled between each of the first and second inner circuit nodes and the intermediate circuit node, and a stabilization circuit having at least one stabilization stage coupled between the intermediate circuit node and the first and second enable terminals and connected to control terminals of the latch transistors for supplying them with suitable control signals so as to ensure their correct turn-on and turn-off during a charge sharing period of the charge pump circuit.

Charge pump circuit

A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.

Charge pump system and corresponding method for managing voltage generation

Protecting the devices of a charge pump includes the connection of a high-voltage transistor between the output node of the charge pump and the load being supplied, and in controlling this transistor with a fraction of the output voltage of the charge pump. This control is accomplished by connecting the control node of the high-voltage transistor to a node of connection between two stages of the multi-stage charge pump onto which a fraction of the controlled output voltage of the multi-stage charge pump is produced. The high-voltage output transistor protects the low voltage devices of the multi-stage charge pump, by preventing the controlled output voltage from undergoing excessively abrupt variations, that could damage the transistors of the last stage of the charge pump.

Multi-stage charge pump voltage generator with protection of the devices of the charge pump

A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Charge-pump with improved biasing of the body regions of the pass-transistors

A single-stage clock booster produces a boosted clock voltage on an output node that is a multiple of a supply voltage. The single-stage clock booster includes a pump capacitor having a first terminal being driven by a first control phase signal. A first switch is controlled by the boosted clock voltage for connecting a second terminal of the pump capacitor to the supply voltage during a charge phase. A second switch connects the second terminal of the pump capacitor to the output node during a boosted clock voltage output phase. A switching circuit alternately connects a control node of the second switch to the supply voltage and to the first terminal of the pump capacitor. The switching circuit is driven by a second control phase signal. A third switch is controlled by a third control phase signal for connecting the output node to a reference voltage during the charge phase.

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Catania, Italy

Carmelo Ucciardello