Infineon Technologies Ag

Carmelo Giunta

Marcus Nuebling

Michael Asam

Steffen Thiele

Markus Winkler

Wolfgang Horchler

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

Slew rate control for fast switching output stages

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

Driver device having an NMOS power transistor and a blocking circuit for stress test mode, and method of stress testing the driver device

A power switch device includes a switch which is configured to switch a load signal between an on state and an off state. A first terminal and a second terminal of the power switch device are configured to provide a supply voltage to the power switch device. The second terminal is further configured to provide a control signal to the power switch device. The control signal is generated by disconnecting the second terminal from an external voltage source. A storage circuit of the power switch device is configured to capacitively store a status of the supply voltage. A control circuit of the power switch device is configured to control operation of the power switch device depending on the stored status of the supply voltage.

Power switch control by supply voltage terminal

A circuit for controlling the switching operation of a transistor is described. A gate driver circuit is operably connected to a control electrode of the transistor and is configured to charge and discharge the control electrode to switch the transistor on and off, respectively, in accordance with a control signal. The charging and discharging of the control electrode is done such that the corresponding transitions in the load current and the output voltage are smooth with a defined slope. A controllable switch is connected to the control electrode such that, when the switch closes, the control electrode is quickly discharged via the switch thus quickly switching off the transistor. A control logic circuit is configured to close the controllable switch for switching off the transistor when at least one of a number of conditions holds true.

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Munich, Germany

Carmelo Giunta