Stmicroelectronics S.r.l.

Carmelo Burgio

Mauro Giacomini

Sergio Lecce

Gaetano Cosentino

Giampiero Borgonovo

Dario Catalano

Walter Girardi

A receiver or transmitter circuit includes a signal propagation path between a radio-frequency (RF) signal node and a baseband processing circuit. Variable gain circuitry is configured to vary a gain applied to a signal propagating between the RF signal node and the baseband processing circuit. The variable gain circuitry varies the gain via first, coarse steps as well as via second, fine steps. This facilitates fine matching of the gains experienced by signals propagating over the in-phase and the quadrature branches in the transmitter and/or receiver circuit.

Automatic gain control circuit, corresponding receiver, transmitter and method

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

Clock recovery method, corresponding circuit and system

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

Method of operating Digital-to-Analog processing chains, corresponding device, apparatus and computer program product

A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

Voltage-regulator circuit, corresponding electronic device and method

Method of operating digital-to-analog processing chains, corresponding device, apparatus and computer program product

In a signal processing chain producing an analog output signal from a digital input signal, dynamic range control applies to the analog output signal a dynamic range control gain as a function of an input gain applied to the digital input signal. The dynamic range control gain is applied to the analog output signal with a delay relative to the input gain applied to the digital input signal. A first flag signal is generated for the analog output signal and a second flag signal for the digital input signal, each flag assuming first and second levels and set to the first level when the signal from which the flag is generated is within a certain amplitude range. The first and second flag signals are compared and delay of application of the dynamic range control gain to the analog output signal controlled as a function of a result of the comparison.

Dynamic range control method and device, apparatus and computer program product

A method of calibrating a thermometer-code SAR-A/D converter is provided. The thermometer-code SAR-A/D converter includes an N-bit digital-to-analog converter (DAC) for outputting an N-bit output code. The DAC includes a first subconverter having a plurality of Nthermometer elements Tand a second subconverter having a plurality of Nbinary-weighted elements. The Noutput code is equal to the sum of Nand Nwhere N=2and Nis equal to N=N. The calibration method includes determining an Integral Non-Linearity error value (&#x3b5;) of an Rthermometer-code level of the thermometer elements. The method further includes reducing the highest of the error value &#x3b5;to obtain a reduced error value, and generating the output code according to said reduced error.

Method of calibrating a thermometer-code SAR A/D converter and thermometer-code SAR-A/D converter implementing said method

The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.

Method of calibrating a SAR A/D converter and SAR-A/D converter implementing said method

A method for processing signals received by a plurality of receiving antennas in a radar system, for example for road safety, which emits sequences of chirp-modulated signals, wherein the received signals are mixed with local replicas of the transmitted signals so as to generate, for each receiving antenna, a sequence of detection signals. The detection signals are subjected to Fourier-transform processing and beam-forming processing for generating values of range, azimuth, and speed for at least one obstacle or 'target' detected by the radar system. The method includes an acquisition process for yielding approximate values of range and azimuth of the obstacle, and a tracking process for yielding accurate range, azimuth and speed values of the obstacle itself.

Method and devices for processing radar signals

Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.

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Bergamo, Italy

Carmelo Burgio