Trilogy Computer Development Partners, Ltd.

Trilogy Systems Corporation

Carlton G Amdahl

James C Lee

Gene M Amdahl

Andrzej Kucharek

John William Sliwa

Richard L Beck

Robert J Beall

Robert M Reinschmidt

John Marshall

Leo Yuan

Anthony Matouk

A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.

Semiconductor chip module interconnection system

A circuit structure, and method for forming the structure, permits wafer scale integration by fabricating plural copies of the circuit in integrated circuit form, and interconnecting predetermined circuit element groups of the copies in a manner that permits a majority voting operation to take place. In this manner, defective circuit elements are masked by being out-voted by corresponding non-defective circuit elements that participate in the voting process. Alternate embodiments of a voter unit, used to implement the voting operation, includes a preferred embodiment that takes advantage of emitter-coupled-logic structure to provide a multiplex, voter, latch combination capable of selectively implementing normal and diagnostic operation. Included in the preferred embodiment of the voter unit is a fused link that implements a repair operation in the event there exists more defective circuit element groups than non-defective circuit element groups participating in the voting process.

Integrated circuit redundancy and method for achieving high-yield

A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic. A plurality of connectors emanate from the ceramic and are electrically coupled by vias or traces through the ceramic to the signal contacts for the transmission of signals to and from the chip.

Module construction for semiconductor chip

A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.

Signal connection system for semiconductor chip

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Saratoga, CA, United States of America

Carlton G Amdahl