Intel Corporation

Carlton E Hanna

Sairam Agraharam

Vasudeva Atluri

Dongming He

Quan Qi

Sujit Sharan

Stephen L Morein

Debendra Mallik

Georg Seidemann

Bernd Waidhas

Sidharth Dalmia

Eytan Mann

Lizabeth Keser

Matthew Escobido

Vijay K Nair

Brian R Butcher

Mark Isenberger

Hitesh Windlass

Dale A Hackitt

Wayne K Ford

Hong Wei Hu

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

Microelectronic assemblies having topside power delivery structures

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

Embodiments are generally directed to module installation on printed circuit boards with embedded trace technology. An embodiment of a printed circuit board includes one or more layers including a top layer; multiple embedded traces that are contained in an area of a surface of a first layer of the one or more layers of the printed circuit board; and a first module, the first module being installed on the plurality of printed traces in the area.

Module installation on printed circuit boards with embedded trace technology

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Partially molded direct chip attach package structures for connectivity module solutions

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.

Integrated antenna for direct chip attach connectivity module package structures

A semiconductor device package having reduced form factor and a method for forming said semiconductor device are disclosed. In an embodiment, an active die is embedded within a cavity in the core layer of the package substrate, wherein an in-situ electromagnetic shield is formed on the sidewalls of the cavity. In another embodiment, a crystal oscillator is at least partially embedded within the core layer of the package substrate. In another embodiment, a package having a component embedded in the core layer is mounted on a PCB, and a crystal oscillator generating a clock frequency for the package is mounted on the PCB. By embedding components within the core or removing components from the package to be mounted directly on the PCB, the x, y, and z dimensions of a package may be reduced. In addition, in-situ electromagnetic shield may reduce EM noise emitted from the active die.

Ultra slim RF package for ultrabooks and smart phones

In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

C4 joint reliability

Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Integrated circuit packages with reduced stress on die and associated methods

An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

Growing community of inventors

Santa Clara, CA, United States of America

Carlton E Hanna